added emulated RAM size parameter

Author: ccattuto

README.md

@@ -40,7 +40,7 @@ This is a simple and readable **RISC-V RV32I emulator** written in pure Python.
 ├── syscalls_newlib.S      # Syscall stubs for Newlib-nano
 ├── linker_bare.ld         # Simple linker script, no heap support
 ├── linker_newlib.ld       # Linker script supporting Newlib-nano
-├── riscv-py.h             # Emulator macros
+├── riscv-py.h             # Emulator macros for user programs
 ├── tests/test_asm*.S      # Example assembly programs
 ├── tests/test_bare*.C     # Example C programs without Newlib support
 ├── tests/test_newlib*.C   # Example C programs with Newlib-nano support
@@ -134,6 +134,7 @@ Argument 3: arg3
 | `--start-checks WHEN` | Condition to enable checks (auto, early, main, first-call, 0xADDR)          |
 | `--init-regs VALUE`   | Initial register state (zero, random, 0xDEADBEEF)                           |
 | `--init-ram PATTERN`  | Initialize RAM with pattern (zero, random, addr, 0xAA)                      |
+| `--ram-size KBS`      | Emulated RAM size (kB, default 1024)                                        |
 | `--timer`             | Enable machine timer                                                        |
 | `--raw-tty`           | Enable raw terminal mode                                                    |
 | `--no-color`          | Remove ANSI colors in debugging output                                      |
@@ -208,7 +209,7 @@ All unit tests from [riscv-samples](https://gitlab.univ-lille.fr/michael.hauspie
 - The emulator relies on ELF symbols for heap management and call tracing: do not strip ELF binaries.
 - When a trap condition is triggered, if `mtvec` is set to zero, the emulator's trap handler is invoked and supports Newlib's system calls. If you install your own trap handler (non-zero `mtvec`), you are responsible for all trap behavior including system calls.
 - `EBREAK` traps with `a7 >= 0xFFFF0000` are used as a debug bridge, regardless of `mtvec`. See `riscv-py.h` for simple logging macros using this facility. These logging macros do not depend on Newlib.
-- The emulated architecure supports unaligned memory accesses and will not trap when they occur.
+- The emulated architecture supports unaligned memory accesses and will not trap when they occur.
 - The 64-bit registers `mtime` and `mtimecmp` are accessible via CSR instructions (rather than being memory-mapped) at addresses `0x7C0` (low 32 bits of `mtime`), `0x7C1` (high 32 bits of `mtime`), `0x7C2` (low 32 bits of `mtimecmp`), and `0x7C3` (high 32 bits of `mtimecmp`). Writes to `mtime` and `mtimecmp` are atomic for the whole 64-bit register and occur when the second word of the register is written.
 
 ###  Performance notes

ram.py

@@ -38,7 +38,7 @@ def initialize_ram(ram, fill='0x00'):
 
 # "Fast" RAM class: no address checks
 class RAM:
-    def __init__(self, size, init=None, logger=None):
+    def __init__(self, size=1024*1024, init=None, logger=None):
         self.memory = bytearray(size)
         self.size = size
         self.logger = logger
@@ -87,7 +87,7 @@ def load_cstring(self, addr, max_len=1024):
 
 # Safe RAM class: checks all addresses
 class SafeRAM:
-    def __init__(self, size, init=None, logger=None):
+    def __init__(self, size=1024*1024, init=None, logger=None):
         self.memory = bytearray(size)
         self.size = size
         self.logger = logger

riscv-emu.py

@@ -24,8 +24,6 @@
 from ram import RAM, SafeRAM
 from syscalls import SyscallHandler
 
-MEMORY_SIZE = 1024 * 1024  # 1 Mb
-
 def parse_args():
     if "--" in sys.argv:
         split_index = sys.argv.index("--")
@@ -51,6 +49,7 @@ def parse_args():
     parser.add_argument("--start-checks", metavar="WHEN", default="auto", help="Condition to enable checks (auto, early, main, first-call, 0xADDR)")
     parser.add_argument("--init-regs", metavar="VALUE", default="zero", help='Initial register state (zero, random, 0xDEADBEEF)')
     parser.add_argument('--init-ram', metavar='PATTERN', default='zero', help='Initialize RAM with pattern (zero, random, addr, 0xAA)')
+    parser.add_argument('--ram-size', metavar="KBS", type=int, default=1024, help='Emulated RAM size (kB, default 1024)')
     parser.add_argument('--timer', action="store_true", help='Enable machine timer')
     parser.add_argument("--raw-tty", action="store_true", help="Raw terminal mode")
     parser.add_argument("--no-color", action="store_false", help="Remove ANSI colors in terminal output")
@@ -107,6 +106,8 @@ def format(self, record):
         args.check_ram = True
         args.check_text = True
 
+    MEMORY_SIZE = 1024 * args.ram_size  # (default 1 Mb)
+
     log = logging.getLogger("riscv-emu")
     log.setLevel(logging.DEBUG)