problem in parsing system verilog files

[tupur25]

openlane 2 is always parsing using verilog front end...I am not able to force it to use system verilog front end...this is creating syntax errors during synthesis which are actually not syntax errors... it seems it is happening because the tag from which the openlane 2 is being pulled doesn't have yosys with uhdm or surelog support...can this be solved?