From 682bd741c39d0b486dd73f96d877eb7dbf0b091e Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Sun, 1 Mar 2026 21:37:39 -0800 Subject: [PATCH 1/2] wire type --- include/Surelog/Design/Signal.h | 8 +++++ src/DesignCompile/CompileHelper.cpp | 6 ++++ src/DesignCompile/NetlistElaboration.cpp | 33 ++++++++++++------- .../tests/CoresSweRVMP/CoresSweRVMP.log | 20 +++++------ 4 files changed, 45 insertions(+), 22 deletions(-) diff --git a/include/Surelog/Design/Signal.h b/include/Surelog/Design/Signal.h index 18f5c1fc79..b657561760 100644 --- a/include/Surelog/Design/Signal.h +++ b/include/Surelog/Design/Signal.h @@ -69,6 +69,10 @@ class Signal final { void setModPort(ModPort* modport) { m_modPort = modport; } void setDirection(VObjectType direction) { m_direction = direction; } void setType(VObjectType type) { m_type = type; } + // For typed net declarations (e.g. "wand integer"), stores the original net + // keyword (paNetType_Wand/Wor/Wire) separate from the data type in m_type. + VObjectType getSubNetType() const { return m_subNetType; } + void setSubNetType(VObjectType t) { m_subNetType = t; } void setDataType(const DataType* dtype) { m_dataType = dtype; } void setPackedDimension(NodeId id) { m_packedDimension = id; } void setUnpackedDimension(NodeId id) { m_unpackedDimension = id; } @@ -116,6 +120,10 @@ class Signal final { const FileContent* m_fileContent = nullptr; NodeId m_nodeId; VObjectType m_type = VObjectType::slNoType; + // Preserved original net keyword for typed net declarations (e.g., "wand integer"). + // When set, m_type holds the data type (e.g., paIntegerAtomType_Integer) and + // m_subNetType holds the net keyword (e.g., paNetType_Wand). + VObjectType m_subNetType = VObjectType::slNoType; VObjectType m_direction = VObjectType::slNoType; ModuleDefinition* m_interfaceDef = nullptr; ModPort* m_modPort = nullptr; diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index bdce482112..0741dabeff 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -2187,6 +2187,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component, sig->setTypespecId(NetType); sig->attributes(attributes); if (isSigned) sig->setSigned(); + // Preserve the original net keyword (e.g. wand/wor) for typed net decls + // like "wand typename". ElaborationStep may later overwrite m_type. + if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype); component->getSignals().push_back(sig); } else { Signal* sig = @@ -2197,6 +2200,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component, sig->setStatic(); sig->attributes(attributes); if (isSigned) sig->setSigned(); + // Preserve the original net keyword (e.g. wand/wor) for typed net decls + // like "wand integer" where nettype was overwritten by the data type. + if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype); component->getSignals().push_back(sig); } diff --git a/src/DesignCompile/NetlistElaboration.cpp b/src/DesignCompile/NetlistElaboration.cpp index e61aba2490..044cc5be78 100644 --- a/src/DesignCompile/NetlistElaboration.cpp +++ b/src/DesignCompile/NetlistElaboration.cpp @@ -1838,6 +1838,10 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, // Nets pass const DataType* dtype = sig->getDataType(); VObjectType subnettype = sig->getType(); + // For typed net declarations (e.g. "wand integer"), the original net keyword + // (paNetType_Wand/Wor/Wire) is preserved in getSubNetType(). The m_type + // (subnettype) holds the data type which may have overridden the net keyword. + VObjectType netKeyword = sig->getSubNetType(); UHDM::typespec* tps = nullptr; // Determine if the "signal" is a net or a var bool isNet = true; @@ -1868,6 +1872,11 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, isNet = true; } } + // Typed net declarations like "wand integer" or "wand typename" store the + // original net keyword in getSubNetType(). Override isNet for these cases. + if (netKeyword != VObjectType::slNoType) { + isNet = true; + } NodeId typeSpecId = sig->getTypeSpecId(); if (typeSpecId) { @@ -1990,7 +1999,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, for (auto a : *sig->attributes()) a->VpiParent(logicn); } logicn->VpiSigned(sig->isSigned()); - logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); // Move range to typespec for simple types // logicn->Ranges(packedDimensions); ref_typespec* rt = s.MakeRef_typespec(); @@ -2106,9 +2115,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, stv->VpiParent(pnets); for (auto r : *packedDimensions) r->VpiParent(pnets); obj = pnets; - pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } else { - stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } } else if (const Struct* st = datatype_cast(dtype)) { struct_net* stv = s.MakeStruct_net(); @@ -2130,9 +2139,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, stv->VpiParent(pnets); for (auto r : *packedDimensions) r->VpiParent(pnets); obj = pnets; - pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } else { - stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } } else if (dtype->getCategory() == DataType::Category::PARAMETER || dtype->getCategory() == DataType::Category::SIMPLE_TYPEDEF) { @@ -2154,7 +2163,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, for (auto a : *sig->attributes()) a->VpiParent(logicn); } logicn->VpiSigned(sig->isSigned()); - logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); // Move range to typespec for simple types // logicn->Ranges(packedDimensions); ref_typespec* rt = s.MakeRef_typespec(); @@ -2185,9 +2194,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, stv->VpiParent(pnets); for (auto r : *packedDimensions) r->VpiParent(pnets); obj = pnets; - pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } else { - stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } } else if (spec->UhdmType() == uhdmenum_typespec) { enum_net* stv = s.MakeEnum_net(); @@ -2210,9 +2219,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, stv->VpiParent(pnets); for (auto r : *packedDimensions) r->VpiParent(pnets); obj = pnets; - pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } else { - stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); } } else if (spec->UhdmType() == uhdmbit_typespec) { bit_var* logicn = s.MakeBit_var(); @@ -2265,7 +2274,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, for (auto a : *sig->attributes()) a->VpiParent(logicn); } logicn->VpiSigned(sig->isSigned()); - logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); ref_typespec* rt = s.MakeRef_typespec(); rt->VpiParent(logicn); rt->Actual_typespec(tps); @@ -2370,7 +2379,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance, } else { logic_net* logicn = s.MakeLogic_net(); logicn->VpiSigned(sig->isSigned()); - logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType())); + logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType())); if (sig->attributes()) { logicn->Attributes(sig->attributes()); for (auto a : *sig->attributes()) a->VpiParent(logicn); diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index b3ba22225d..d868125098 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -64,22 +64,22 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv -[ 18%] Generating 12_beh_lib.sv -[ 18%] Generating 11_ifu_bp_ctl.sv -[ 25%] Generating 14_mem_lib.sv -[ 31%] Generating 13_ifu_mem_ctl.sv -[ 37%] Generating 15_exu.sv +[ 6%] Generating 14_mem_lib.sv +[ 12%] Generating 10_lsu_bus_intf.sv +[ 18%] Generating 13_ifu_mem_ctl.sv +[ 25%] Generating 15_exu.sv +[ 37%] Generating 11_ifu_bp_ctl.sv +[ 37%] Generating 12_beh_lib.sv [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv -[ 81%] Generating 6_dbg.sv -[ 93%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 9_tb_top.sv -[100%] Generating 8_ifu_aln_ctl.sv +[ 81%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 8_ifu_aln_ctl.sv +[ 93%] Generating 6_dbg.sv +[100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". From 98ffd455ee1244f8b51b710b78ebfc113bd600fb Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Sun, 1 Mar 2026 22:25:08 -0800 Subject: [PATCH 2/2] wire type --- tests/WireType/WireType.log | 2847 +++++++++++++++++++++++++++++++++++ tests/WireType/WireType.sl | 1 + tests/WireType/dut.sv | 34 + 3 files changed, 2882 insertions(+) create mode 100644 tests/WireType/WireType.log create mode 100644 tests/WireType/WireType.sl create mode 100644 tests/WireType/dut.sv diff --git a/tests/WireType/WireType.log b/tests/WireType/WireType.log new file mode 100644 index 0000000000..6f90b794b7 --- /dev/null +++ b/tests/WireType/WireType.log @@ -0,0 +1,2847 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/WireType/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/WireType/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<728> s<727> l<1:1> el<1:0> +n u<2> t p<4> s<3> l<1:1> el<1:7> +n u<3> t p<4> l<1:8> el<1:11> +n<> u<4> t p<725> c<2> s<17> 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c<144> l<5:55> el<5:79> +n<> u<146> t p<725> c<145> s<159> l<5:55> el<5:79> +n<> u<147> t p<154> s<150> l<6:5> el<6:8> +n<> u<148> t p<149> l<6:9> el<6:14> +n<> u<149> t p<150> c<148> l<6:9> el<6:14> +n<> u<150> t p<154> c<149> s<153> l<6:9> el<6:14> +n u<151> t p<152> l<6:15> el<6:26> +n<> u<152> t p<153> c<151> l<6:15> el<6:26> +n<> u<153> t p<154> c<152> l<6:15> el<6:26> +n<> u<154> t p<155> c<147> l<6:5> el<6:27> +n<> u<155> t p<156> c<154> l<6:5> el<6:27> +n<> u<156> t p<157> c<155> l<6:5> el<6:27> +n<> u<157> t p<158> c<156> l<6:5> el<6:27> +n<> u<158> t p<159> c<157> l<6:5> el<6:27> +n<> u<159> t p<725> c<158> s<174> l<6:5> el<6:27> +n u<160> t p<161> l<6:35> el<6:46> +n<> u<161> t p<164> c<160> s<163> l<6:35> el<6:46> +n<> u<162> t p<163> l<6:47> el<6:47> +n<> u<163> t p<164> c<162> l<6:47> el<6:47> +n<> u<164> t p<169> c<161> s<168> l<6:35> el<6:46> +n<0> u<165> t p<166> l<6:49> el<6:50> +n<> u<166> t p<167> c<165> l<6:49> el<6:50> +n<> u<167> t p<168> c<166> l<6:49> el<6:50> +n<> u<168> t p<169> c<167> l<6:49> el<6:50> +n<> u<169> t p<170> c<164> l<6:35> el<6:50> +n<> u<170> t p<171> c<169> l<6:35> el<6:50> +n<> u<171> t p<172> c<170> l<6:28> el<6:51> +n<> u<172> t p<173> c<171> l<6:28> el<6:51> +n<> u<173> t p<174> c<172> l<6:28> el<6:51> +n<> u<174> t p<725> c<173> s<189> l<6:28> el<6:51> +n u<175> t p<176> l<6:59> el<6:70> +n<> u<176> t p<179> c<175> s<178> l<6:59> el<6:70> +n<> u<177> t p<178> l<6:71> el<6:71> +n<> u<178> t p<179> c<177> l<6:71> el<6:71> +n<> u<179> t p<184> c<176> s<183> l<6:59> el<6:70> +n<0> u<180> t p<181> l<6:73> el<6:74> +n<> u<181> t p<182> c<180> l<6:73> el<6:74> +n<> u<182> t p<183> c<181> l<6:73> el<6:74> +n<> u<183> t p<184> c<182> l<6:73> el<6:74> +n<> u<184> t p<185> c<179> l<6:59> el<6:74> +n<> u<185> t p<186> c<184> l<6:59> el<6:74> +n<> u<186> t p<187> c<185> l<6:52> el<6:75> +n<> u<187> t p<188> c<186> l<6:52> el<6:75> +n<> u<188> t p<189> c<187> l<6:52> el<6:75> +n<> u<189> t p<725> c<188> s<202> l<6:52> el<6:75> +n<> u<190> t p<197> s<193> l<7:5> el<7:8> +n<> u<191> t p<192> l<7:9> el<7:14> +n<> u<192> t p<193> c<191> l<7:9> el<7:14> +n<> u<193> t p<197> c<192> s<196> l<7:9> el<7:14> +n u<194> t p<195> l<7:15> el<7:26> +n<> u<195> t p<196> c<194> l<7:15> el<7:26> +n<> u<196> t p<197> c<195> l<7:15> el<7:26> +n<> u<197> t p<198> c<190> l<7:5> el<7:27> +n<> u<198> t p<199> c<197> l<7:5> el<7:27> +n<> u<199> t p<200> c<198> l<7:5> el<7:27> +n<> u<200> t p<201> c<199> l<7:5> el<7:27> +n<> u<201> t p<202> c<200> l<7:5> el<7:27> +n<> u<202> t p<725> c<201> s<217> l<7:5> el<7:27> +n u<203> t p<204> l<7:35> el<7:46> +n<> u<204> t p<207> c<203> s<206> l<7:35> el<7:46> +n<> u<205> t p<206> l<7:47> el<7:47> +n<> u<206> t p<207> c<205> l<7:47> el<7:47> +n<> u<207> t p<212> c<204> s<211> l<7:35> el<7:46> +n<1> u<208> t p<209> l<7:49> el<7:50> +n<> u<209> t p<210> c<208> l<7:49> el<7:50> +n<> u<210> t p<211> c<209> l<7:49> el<7:50> +n<> u<211> t p<212> c<210> l<7:49> el<7:50> +n<> u<212> t p<213> c<207> l<7:35> el<7:50> +n<> u<213> t p<214> c<212> l<7:35> el<7:50> +n<> u<214> t p<215> c<213> l<7:28> el<7:51> +n<> u<215> t p<216> c<214> l<7:28> el<7:51> +n<> u<216> t p<217> c<215> l<7:28> el<7:51> +n<> u<217> t p<725> c<216> s<232> l<7:28> el<7:51> +n u<218> t p<219> l<7:59> el<7:70> +n<> u<219> t p<222> c<218> s<221> l<7:59> el<7:70> +n<> u<220> t p<221> l<7:71> el<7:71> +n<> u<221> t p<222> c<220> l<7:71> el<7:71> +n<> u<222> t p<227> c<219> s<226> l<7:59> el<7:70> +n<0> u<223> t p<224> l<7:73> el<7:74> +n<> u<224> t p<225> c<223> l<7:73> el<7:74> +n<> u<225> t p<226> c<224> l<7:73> el<7:74> +n<> u<226> t p<227> c<225> l<7:73> el<7:74> +n<> u<227> t p<228> c<222> l<7:59> el<7:74> +n<> u<228> t p<229> c<227> l<7:59> el<7:74> +n<> u<229> t p<230> c<228> l<7:52> el<7:75> +n<> u<230> t p<231> c<229> l<7:52> el<7:75> +n<> u<231> t p<232> c<230> l<7:52> el<7:75> +n<> u<232> t p<725> c<231> s<245> l<7:52> el<7:75> +n<> u<233> t p<240> s<236> l<9:5> el<9:9> +n<> u<234> t p<235> l<9:10> el<9:17> +n<> u<235> t p<236> c<234> l<9:10> el<9:17> +n<> u<236> t p<240> c<235> s<239> l<9:10> el<9:17> +n u<237> t p<238> l<9:18> el<9:30> +n<> u<238> t p<239> c<237> l<9:18> el<9:30> +n<> u<239> t p<240> c<238> l<9:18> el<9:30> +n<> u<240> t p<241> c<233> l<9:5> el<9:31> +n<> u<241> t p<242> c<240> l<9:5> el<9:31> +n<> u<242> t p<243> c<241> l<9:5> el<9:31> +n<> u<243> t p<244> c<242> l<9:5> el<9:31> +n<> u<244> t p<245> c<243> l<9:5> el<9:31> +n<> u<245> t p<725> c<244> s<260> l<9:5> el<9:31> +n u<246> t p<247> l<9:39> el<9:51> +n<> u<247> t p<250> c<246> s<249> l<9:39> el<9:51> +n<> u<248> t p<249> l<9:52> el<9:52> +n<> u<249> t p<250> c<248> l<9:52> el<9:52> +n<> u<250> t p<255> c<247> s<254> l<9:39> el<9:51> +n<4'b1001> u<251> t p<252> l<9:54> el<9:61> +n<> u<252> t p<253> c<251> l<9:54> el<9:61> +n<> u<253> t p<254> c<252> l<9:54> el<9:61> +n<> u<254> t p<255> c<253> l<9:54> el<9:61> +n<> u<255> t p<256> c<250> l<9:39> el<9:61> +n<> u<256> t p<257> c<255> l<9:39> el<9:61> +n<> u<257> t p<258> c<256> l<9:32> el<9:62> +n<> u<258> t p<259> c<257> l<9:32> el<9:62> +n<> u<259> t p<260> c<258> l<9:32> el<9:62> +n<> u<260> t p<725> c<259> s<273> l<9:32> el<9:62> +n<> u<261> t p<268> s<264> l<10:5> el<10:9> +n<> u<262> t p<263> l<10:10> el<10:17> +n<> u<263> t p<264> c<262> l<10:10> el<10:17> +n<> u<264> t p<268> c<263> s<267> l<10:10> el<10:17> +n u<265> t p<266> l<10:18> el<10:30> +n<> u<266> t p<267> c<265> l<10:18> el<10:30> +n<> u<267> t p<268> c<266> l<10:18> el<10:30> +n<> u<268> t p<269> c<261> l<10:5> el<10:31> +n<> u<269> t p<270> c<268> l<10:5> el<10:31> +n<> u<270> t p<271> c<269> l<10:5> el<10:31> +n<> u<271> t p<272> c<270> l<10:5> el<10:31> +n<> u<272> t p<273> c<271> l<10:5> el<10:31> +n<> u<273> t p<725> c<272> s<288> l<10:5> el<10:31> +n u<274> t p<275> l<10:39> el<10:51> +n<> u<275> t p<278> c<274> s<277> l<10:39> el<10:51> +n<> u<276> t p<277> l<10:52> el<10:52> +n<> u<277> t p<278> c<276> l<10:52> el<10:52> +n<> u<278> t p<283> c<275> s<282> l<10:39> el<10:51> +n<4'b1001> u<279> t p<280> l<10:54> el<10:61> +n<> u<280> t p<281> c<279> l<10:54> el<10:61> +n<> u<281> t p<282> c<280> l<10:54> el<10:61> +n<> u<282> t p<283> c<281> l<10:54> el<10:61> +n<> u<283> t p<284> c<278> l<10:39> el<10:61> +n<> u<284> t p<285> c<283> l<10:39> el<10:61> +n<> u<285> t p<286> c<284> l<10:32> el<10:62> +n<> u<286> t p<287> c<285> l<10:32> el<10:62> +n<> u<287> t p<288> c<286> l<10:32> el<10:62> +n<> u<288> t p<725> c<287> s<303> l<10:32> el<10:62> +n u<289> t p<290> l<10:70> el<10:82> +n<> u<290> t p<293> c<289> s<292> l<10:70> el<10:82> +n<> u<291> t p<292> l<10:83> el<10:83> +n<> u<292> t p<293> c<291> l<10:83> el<10:83> +n<> u<293> t p<298> c<290> s<297> l<10:70> el<10:82> +n<4'b1010> u<294> t p<295> l<10:85> el<10:92> +n<> u<295> t p<296> c<294> l<10:85> el<10:92> +n<> u<296> t p<297> c<295> l<10:85> el<10:92> +n<> u<297> t p<298> c<296> l<10:85> el<10:92> +n<> u<298> t p<299> c<293> l<10:70> el<10:92> +n<> u<299> t p<300> c<298> l<10:70> el<10:92> +n<> u<300> t p<301> c<299> l<10:63> el<10:93> +n<> u<301> t p<302> c<300> l<10:63> el<10:93> +n<> u<302> t p<303> c<301> l<10:63> el<10:93> +n<> u<303> t p<725> c<302> s<316> l<10:63> el<10:93> +n<> u<304> t p<311> s<307> l<11:5> el<11:8> +n<> u<305> t p<306> l<11:9> el<11:16> +n<> u<306> t p<307> c<305> l<11:9> el<11:16> +n<> u<307> t p<311> c<306> s<310> l<11:9> el<11:16> +n u<308> t p<309> l<11:17> el<11:28> +n<> u<309> t p<310> c<308> l<11:17> el<11:28> +n<> u<310> t p<311> c<309> l<11:17> el<11:28> +n<> u<311> t p<312> c<304> l<11:5> el<11:29> +n<> u<312> t p<313> c<311> l<11:5> el<11:29> +n<> u<313> t p<314> c<312> l<11:5> el<11:29> +n<> u<314> t p<315> c<313> l<11:5> el<11:29> +n<> u<315> t p<316> c<314> l<11:5> el<11:29> +n<> u<316> t p<725> c<315> s<331> l<11:5> el<11:29> +n u<317> t p<318> l<11:37> el<11:48> +n<> u<318> t p<321> c<317> s<320> l<11:37> el<11:48> +n<> u<319> t p<320> l<11:49> el<11:49> +n<> u<320> t p<321> c<319> l<11:49> el<11:49> +n<> u<321> t p<326> c<318> s<325> l<11:37> el<11:48> +n<4'b1001> u<322> t p<323> l<11:51> el<11:58> +n<> u<323> t p<324> c<322> l<11:51> el<11:58> +n<> u<324> t p<325> c<323> l<11:51> el<11:58> +n<> u<325> t p<326> c<324> l<11:51> el<11:58> +n<> u<326> t p<327> c<321> l<11:37> el<11:58> +n<> u<327> t p<328> c<326> l<11:37> el<11:58> +n<> u<328> t p<329> c<327> l<11:30> el<11:59> +n<> u<329> t p<330> c<328> l<11:30> el<11:59> +n<> u<330> t p<331> c<329> l<11:30> el<11:59> +n<> u<331> t p<725> c<330> s<346> l<11:30> el<11:59> +n u<332> t p<333> l<11:67> el<11:78> +n<> u<333> t p<336> c<332> s<335> l<11:67> el<11:78> +n<> u<334> t p<335> l<11:79> el<11:79> +n<> u<335> t p<336> c<334> l<11:79> el<11:79> +n<> u<336> t p<341> c<333> s<340> l<11:67> el<11:78> +n<4'b1010> u<337> t p<338> l<11:81> el<11:88> +n<> u<338> t p<339> c<337> l<11:81> el<11:88> +n<> u<339> t p<340> c<338> l<11:81> el<11:88> +n<> u<340> t p<341> c<339> l<11:81> el<11:88> +n<> u<341> t p<342> c<336> l<11:67> el<11:88> +n<> u<342> t p<343> c<341> l<11:67> el<11:88> +n<> u<343> t p<344> c<342> l<11:60> el<11:89> +n<> u<344> t p<345> c<343> l<11:60> el<11:89> +n<> u<345> t p<346> c<344> l<11:60> el<11:89> +n<> u<346> t p<725> c<345> s<366> l<11:60> el<11:89> +n<> u<347> t p<358> s<357> l<13:13> el<13:18> +n<3> u<348> t p<349> l<13:20> el<13:21> +n<> u<349> t p<350> c<348> l<13:20> el<13:21> +n<> u<350> t p<351> c<349> l<13:20> el<13:21> +n<> u<351> t p<356> c<350> s<355> l<13:20> el<13:21> +n<0> u<352> t p<353> l<13:22> el<13:23> +n<> u<353> t p<354> c<352> l<13:22> el<13:23> +n<> u<354> t p<355> c<353> l<13:22> el<13:23> +n<> u<355> t p<356> c<354> l<13:22> el<13:23> +n<> u<356> t p<357> c<351> l<13:20> el<13:23> +n<> u<357> t p<358> c<356> l<13:19> el<13:24> +n<> u<358> t p<360> c<347> s<359> l<13:13> el<13:24> +n u<359> t p<360> l<13:25> el<13:33> +n<> u<360> t p<361> c<358> l<13:5> el<13:34> +n<> u<361> t p<362> c<360> l<13:5> el<13:34> +n<> u<362> t p<363> c<361> l<13:5> el<13:34> +n<> u<363> t p<364> c<362> l<13:5> el<13:34> +n<> u<364> t p<365> c<363> l<13:5> el<13:34> +n<> u<365> t p<366> c<364> l<13:5> el<13:34> +n<> u<366> t p<725> c<365> s<379> l<13:5> el<13:34> +n<> u<367> t p<374> s<370> l<14:5> el<14:9> +n u<368> t p<369> l<14:10> el<14:18> +n<> u<369> t p<370> c<368> l<14:10> el<14:18> +n<> u<370> t p<374> c<369> s<373> l<14:10> el<14:18> +n u<371> t p<372> l<14:19> el<14:32> +n<> u<372> t p<373> c<371> l<14:19> el<14:32> +n<> u<373> t p<374> c<372> l<14:19> el<14:32> +n<> u<374> t p<375> c<367> l<14:5> el<14:33> +n<> u<375> t p<376> c<374> l<14:5> el<14:33> +n<> u<376> t p<377> c<375> l<14:5> el<14:33> +n<> u<377> t p<378> c<376> l<14:5> el<14:33> +n<> u<378> t p<379> c<377> l<14:5> el<14:33> +n<> u<379> t p<725> c<378> s<394> l<14:5> el<14:33> +n u<380> t p<381> l<14:41> el<14:54> +n<> u<381> t p<384> c<380> s<383> l<14:41> el<14:54> +n<> u<382> t p<383> l<14:55> el<14:55> +n<> u<383> t p<384> c<382> l<14:55> el<14:55> +n<> u<384> t p<389> c<381> s<388> l<14:41> el<14:54> +n<4'b1001> u<385> t p<386> l<14:57> el<14:64> +n<> u<386> t p<387> c<385> l<14:57> el<14:64> +n<> u<387> t p<388> c<386> l<14:57> el<14:64> +n<> u<388> t p<389> c<387> l<14:57> el<14:64> +n<> u<389> t p<390> c<384> l<14:41> el<14:64> +n<> u<390> t p<391> c<389> l<14:41> el<14:64> +n<> u<391> t p<392> c<390> l<14:34> el<14:65> +n<> u<392> t p<393> c<391> l<14:34> el<14:65> +n<> u<393> t p<394> c<392> l<14:34> el<14:65> +n<> u<394> t p<725> c<393> s<407> l<14:34> el<14:65> +n<> u<395> t p<402> s<398> l<15:5> el<15:9> +n u<396> t p<397> l<15:10> el<15:18> +n<> u<397> t p<398> c<396> l<15:10> el<15:18> +n<> u<398> t p<402> c<397> s<401> l<15:10> el<15:18> +n u<399> t p<400> l<15:19> el<15:32> +n<> u<400> t p<401> c<399> l<15:19> el<15:32> +n<> u<401> t p<402> c<400> l<15:19> el<15:32> +n<> u<402> t p<403> c<395> l<15:5> el<15:33> +n<> u<403> t p<404> c<402> l<15:5> el<15:33> +n<> u<404> t p<405> c<403> l<15:5> el<15:33> +n<> u<405> t p<406> c<404> l<15:5> el<15:33> +n<> u<406> t p<407> c<405> l<15:5> el<15:33> +n<> u<407> t p<725> c<406> s<422> l<15:5> el<15:33> +n u<408> t p<409> l<15:41> el<15:54> +n<> u<409> t p<412> c<408> s<411> l<15:41> el<15:54> +n<> u<410> t p<411> l<15:55> el<15:55> +n<> u<411> t p<412> c<410> l<15:55> el<15:55> +n<> u<412> t p<417> c<409> s<416> l<15:41> el<15:54> +n<4'b1001> u<413> t p<414> l<15:57> el<15:64> +n<> u<414> t p<415> c<413> l<15:57> el<15:64> +n<> u<415> t p<416> c<414> l<15:57> el<15:64> +n<> u<416> t p<417> c<415> l<15:57> el<15:64> +n<> u<417> t p<418> c<412> l<15:41> el<15:64> +n<> u<418> t p<419> c<417> l<15:41> el<15:64> +n<> u<419> t p<420> c<418> l<15:34> el<15:65> +n<> u<420> t p<421> c<419> l<15:34> el<15:65> +n<> u<421> t p<422> c<420> l<15:34> el<15:65> +n<> u<422> t p<725> c<421> s<437> l<15:34> el<15:65> +n u<423> t p<424> l<15:73> el<15:86> +n<> u<424> t p<427> c<423> s<426> l<15:73> el<15:86> +n<> u<425> t p<426> l<15:87> el<15:87> +n<> u<426> t p<427> c<425> l<15:87> el<15:87> +n<> u<427> t p<432> c<424> s<431> l<15:73> el<15:86> +n<4'b1010> u<428> t p<429> l<15:89> el<15:96> +n<> u<429> t p<430> c<428> l<15:89> el<15:96> +n<> u<430> t p<431> c<429> l<15:89> el<15:96> +n<> u<431> t p<432> c<430> l<15:89> el<15:96> +n<> u<432> t p<433> c<427> l<15:73> el<15:96> +n<> u<433> t p<434> c<432> l<15:73> el<15:96> +n<> u<434> t p<435> c<433> l<15:66> el<15:97> +n<> u<435> t p<436> c<434> l<15:66> el<15:97> +n<> u<436> t p<437> c<435> l<15:66> el<15:97> +n<> u<437> t p<725> c<436> s<450> l<15:66> el<15:97> +n<> u<438> t p<445> s<441> l<16:5> el<16:8> +n u<439> t p<440> l<16:9> el<16:17> +n<> u<440> t p<441> c<439> l<16:9> el<16:17> +n<> u<441> t p<445> c<440> s<444> l<16:9> el<16:17> +n u<442> t p<443> l<16:18> el<16:30> +n<> u<443> t p<444> c<442> l<16:18> el<16:30> +n<> u<444> t p<445> c<443> l<16:18> el<16:30> +n<> u<445> t p<446> c<438> l<16:5> el<16:31> +n<> u<446> t p<447> c<445> l<16:5> el<16:31> +n<> u<447> t p<448> c<446> l<16:5> el<16:31> +n<> u<448> t p<449> c<447> l<16:5> el<16:31> +n<> u<449> t p<450> c<448> l<16:5> el<16:31> +n<> u<450> t p<725> c<449> s<465> l<16:5> el<16:31> +n u<451> t p<452> l<16:39> el<16:51> +n<> u<452> t p<455> c<451> s<454> l<16:39> el<16:51> +n<> u<453> t p<454> l<16:52> el<16:52> +n<> u<454> t p<455> c<453> l<16:52> el<16:52> +n<> u<455> t p<460> c<452> s<459> l<16:39> el<16:51> +n<4'b1001> u<456> t p<457> l<16:54> el<16:61> +n<> u<457> t p<458> c<456> l<16:54> el<16:61> +n<> u<458> t p<459> c<457> l<16:54> el<16:61> +n<> u<459> t p<460> c<458> l<16:54> el<16:61> +n<> u<460> t p<461> c<455> l<16:39> el<16:61> +n<> u<461> t p<462> c<460> l<16:39> el<16:61> +n<> u<462> t p<463> c<461> l<16:32> el<16:62> +n<> u<463> t p<464> c<462> l<16:32> el<16:62> +n<> u<464> t p<465> c<463> l<16:32> el<16:62> +n<> u<465> t p<725> c<464> s<480> l<16:32> el<16:62> +n u<466> t p<467> l<16:70> el<16:82> +n<> u<467> t p<470> c<466> s<469> l<16:70> el<16:82> +n<> u<468> t p<469> l<16:83> el<16:83> +n<> u<469> t p<470> c<468> l<16:83> el<16:83> +n<> u<470> t p<475> c<467> s<474> l<16:70> el<16:82> +n<4'b1010> u<471> t p<472> l<16:85> el<16:92> +n<> u<472> t p<473> c<471> l<16:85> el<16:92> +n<> u<473> t p<474> c<472> l<16:85> el<16:92> +n<> u<474> t p<475> c<473> l<16:85> el<16:92> +n<> u<475> t p<476> c<470> l<16:70> el<16:92> +n<> u<476> t p<477> c<475> l<16:70> el<16:92> +n<> u<477> t p<478> c<476> l<16:63> el<16:93> +n<> u<478> t p<479> c<477> l<16:63> el<16:93> +n<> u<479> t p<480> c<478> l<16:63> el<16:93> +n<> u<480> t p<725> c<479> s<723> l<16:63> el<16:93> +n<> u<481> t p<720> s<719> l<18:5> el<18:11> +n<> u<482> t p<483> l<18:12> el<18:14> +n<> u<483> t p<717> c<482> s<716> l<18:12> el<18:14> +n u<484> t p<485> l<19:17> el<19:29> +n<> u<485> t p<486> c<484> l<19:17> el<19:29> +n<> u<486> t p<487> c<485> l<19:17> el<19:29> +n<> u<487> t p<493> c<486> s<492> l<19:17> el<19:29> +n<0> u<488> t p<489> l<19:33> el<19:34> +n<> u<489> t p<490> c<488> l<19:33> el<19:34> +n<> u<490> t p<491> c<489> l<19:33> el<19:34> +n<> u<491> t p<493> c<490> l<19:33> el<19:34> +n<> u<492> t p<493> s<491> l<19:30> el<19:32> +n<> u<493> t p<496> c<487> s<495> l<19:17> el<19:34> +n<> u<494> t p<495> l<19:35> el<19:36> +n<> u<495> t p<496> c<494> l<19:35> el<19:36> +n<> u<496> t p<497> c<493> l<19:9> el<19:36> +n<> u<497> t p<498> c<496> l<19:9> el<19:36> +n<> u<498> t p<499> c<497> l<19:9> el<19:36> +n<> u<499> t p<500> c<498> l<19:9> el<19:36> +n<> u<500> t p<501> c<499> l<19:9> el<19:36> +n<> u<501> t p<502> c<500> l<19:9> el<19:36> +n<> u<502> t p<713> c<501> s<521> l<19:9> el<19:36> +n u<503> t p<504> l<20:17> el<20:29> +n<> u<504> t p<505> c<503> l<20:17> el<20:29> +n<> u<505> t p<506> c<504> l<20:17> el<20:29> +n<> u<506> t p<512> c<505> s<511> l<20:17> el<20:29> +n<1> u<507> t p<508> l<20:33> el<20:34> +n<> u<508> t p<509> c<507> l<20:33> el<20:34> +n<> u<509> t p<510> c<508> l<20:33> el<20:34> +n<> u<510> t p<512> c<509> l<20:33> el<20:34> +n<> u<511> t p<512> s<510> l<20:30> el<20:32> +n<> u<512> t p<515> c<506> s<514> l<20:17> el<20:34> +n<> u<513> t p<514> l<20:35> el<20:36> +n<> u<514> t p<515> c<513> l<20:35> el<20:36> +n<> u<515> t p<516> c<512> l<20:9> el<20:36> +n<> u<516> t p<517> c<515> l<20:9> el<20:36> +n<> u<517> t p<518> c<516> l<20:9> el<20:36> +n<> u<518> t p<519> c<517> l<20:9> el<20:36> +n<> u<519> t p<520> c<518> l<20:9> el<20:36> +n<> u<520> t p<521> c<519> l<20:9> el<20:36> +n<> u<521> t p<713> c<520> s<540> l<20:9> el<20:36> +n u<522> t p<523> l<21:17> el<21:29> +n<> u<523> t p<524> c<522> l<21:17> el<21:29> +n<> u<524> t p<525> c<523> l<21:17> el<21:29> +n<> u<525> t p<531> c<524> s<530> l<21:17> el<21:29> +n<0> u<526> t p<527> l<21:33> el<21:34> +n<> u<527> t p<528> c<526> l<21:33> el<21:34> +n<> u<528> t p<529> c<527> l<21:33> el<21:34> +n<> u<529> t p<531> c<528> l<21:33> el<21:34> +n<> u<530> t p<531> s<529> l<21:30> el<21:32> +n<> u<531> t p<534> c<525> s<533> l<21:17> el<21:34> +n<> u<532> t p<533> l<21:35> el<21:36> +n<> u<533> t p<534> c<532> l<21:35> el<21:36> +n<> u<534> t p<535> c<531> l<21:9> el<21:36> +n<> u<535> t p<536> c<534> l<21:9> el<21:36> +n<> u<536> t p<537> c<535> l<21:9> el<21:36> +n<> u<537> t p<538> c<536> l<21:9> el<21:36> +n<> u<538> t p<539> c<537> l<21:9> el<21:36> +n<> u<539> t p<540> c<538> l<21:9> el<21:36> +n<> u<540> t p<713> c<539> s<559> l<21:9> el<21:36> +n u<541> t p<542> l<22:17> el<22:29> +n<> u<542> t p<543> c<541> l<22:17> el<22:29> +n<> u<543> t p<544> c<542> l<22:17> el<22:29> +n<> u<544> t p<550> c<543> s<549> l<22:17> el<22:29> +n<1> u<545> t p<546> l<22:33> el<22:34> +n<> u<546> t p<547> c<545> l<22:33> el<22:34> +n<> u<547> t p<548> c<546> l<22:33> el<22:34> +n<> u<548> t p<550> c<547> l<22:33> el<22:34> +n<> u<549> t p<550> s<548> l<22:30> el<22:32> +n<> u<550> t p<553> c<544> s<552> l<22:17> el<22:34> +n<> u<551> t p<552> l<22:35> el<22:36> +n<> u<552> t p<553> c<551> l<22:35> el<22:36> +n<> u<553> t p<554> c<550> l<22:9> el<22:36> +n<> u<554> t p<555> c<553> l<22:9> el<22:36> +n<> u<555> t p<556> c<554> l<22:9> el<22:36> +n<> u<556> t p<557> c<555> l<22:9> el<22:36> +n<> u<557> t p<558> c<556> l<22:9> el<22:36> +n<> u<558> t p<559> c<557> l<22:9> el<22:36> +n<> u<559> t p<713> c<558> s<578> l<22:9> el<22:36> +n u<560> t p<561> l<23:17> el<23:28> +n<> u<561> t p<562> c<560> l<23:17> el<23:28> +n<> u<562> t p<563> c<561> l<23:17> el<23:28> +n<> u<563> t p<569> c<562> s<568> l<23:17> el<23:28> +n<0> u<564> t p<565> l<23:32> el<23:33> +n<> u<565> t p<566> c<564> l<23:32> el<23:33> +n<> u<566> t p<567> c<565> l<23:32> el<23:33> +n<> u<567> t p<569> c<566> l<23:32> el<23:33> +n<> u<568> t p<569> s<567> l<23:29> el<23:31> +n<> u<569> t p<572> c<563> s<571> l<23:17> el<23:33> +n<> u<570> t p<571> l<23:34> el<23:35> +n<> u<571> t p<572> c<570> l<23:34> el<23:35> +n<> u<572> t p<573> c<569> l<23:9> el<23:35> +n<> u<573> t p<574> c<572> l<23:9> el<23:35> +n<> u<574> t p<575> c<573> l<23:9> el<23:35> +n<> u<575> t p<576> c<574> l<23:9> el<23:35> +n<> u<576> t p<577> c<575> l<23:9> el<23:35> +n<> u<577> t p<578> c<576> l<23:9> el<23:35> +n<> u<578> t p<713> c<577> s<597> l<23:9> el<23:35> +n u<579> t p<580> l<24:17> el<24:28> +n<> u<580> t p<581> c<579> l<24:17> el<24:28> +n<> u<581> t p<582> c<580> l<24:17> el<24:28> +n<> u<582> t p<588> c<581> s<587> l<24:17> el<24:28> +n<1> u<583> t p<584> l<24:32> el<24:33> +n<> u<584> t p<585> c<583> l<24:32> el<24:33> +n<> u<585> t p<586> c<584> l<24:32> el<24:33> +n<> u<586> t p<588> c<585> l<24:32> el<24:33> +n<> u<587> t p<588> s<586> l<24:29> el<24:31> +n<> u<588> t p<591> c<582> s<590> l<24:17> el<24:33> +n<> u<589> t p<590> l<24:34> el<24:35> +n<> u<590> t p<591> c<589> l<24:34> el<24:35> +n<> u<591> t p<592> c<588> l<24:9> el<24:35> +n<> u<592> t p<593> c<591> l<24:9> el<24:35> +n<> u<593> t p<594> c<592> l<24:9> el<24:35> +n<> u<594> t p<595> c<593> l<24:9> el<24:35> +n<> u<595> t p<596> c<594> l<24:9> el<24:35> +n<> u<596> t p<597> c<595> l<24:9> el<24:35> +n<> u<597> t p<713> c<596> s<616> l<24:9> el<24:35> +n u<598> t p<599> l<26:17> el<26:29> +n<> u<599> t p<600> c<598> l<26:17> el<26:29> +n<> u<600> t p<601> c<599> l<26:17> el<26:29> +n<> u<601> t p<607> c<600> s<606> l<26:17> el<26:29> +n<4'b1001> u<602> t p<603> l<26:33> el<26:40> +n<> u<603> t p<604> c<602> l<26:33> el<26:40> +n<> u<604> t p<605> c<603> l<26:33> el<26:40> +n<> u<605> t p<607> c<604> l<26:33> el<26:40> +n<> u<606> t p<607> s<605> l<26:30> el<26:32> +n<> u<607> t p<610> c<601> s<609> l<26:17> el<26:40> +n<> u<608> t p<609> l<26:41> el<26:42> +n<> u<609> t p<610> c<608> l<26:41> el<26:42> +n<> u<610> t p<611> c<607> l<26:9> el<26:42> +n<> u<611> t p<612> c<610> l<26:9> el<26:42> +n<> u<612> t p<613> c<611> l<26:9> el<26:42> +n<> u<613> t p<614> c<612> l<26:9> el<26:42> +n<> u<614> t p<615> c<613> l<26:9> el<26:42> +n<> u<615> t p<616> c<614> l<26:9> el<26:42> +n<> u<616> t p<713> c<615> s<635> l<26:9> el<26:42> +n u<617> t p<618> l<27:17> el<27:29> +n<> u<618> t p<619> c<617> l<27:17> el<27:29> +n<> u<619> t p<620> c<618> l<27:17> el<27:29> +n<> u<620> t p<626> c<619> s<625> l<27:17> el<27:29> +n<4'b1000> u<621> t p<622> l<27:33> el<27:40> +n<> u<622> t p<623> c<621> l<27:33> el<27:40> +n<> u<623> t p<624> c<622> l<27:33> el<27:40> +n<> u<624> t p<626> c<623> l<27:33> el<27:40> +n<> u<625> t p<626> s<624> l<27:30> el<27:32> +n<> u<626> t p<629> c<620> s<628> l<27:17> el<27:40> +n<> u<627> t p<628> l<27:41> el<27:42> +n<> u<628> t p<629> c<627> l<27:41> el<27:42> +n<> u<629> t p<630> c<626> l<27:9> el<27:42> +n<> u<630> t p<631> c<629> l<27:9> el<27:42> +n<> u<631> t p<632> c<630> l<27:9> el<27:42> +n<> u<632> t p<633> c<631> l<27:9> el<27:42> +n<> u<633> t p<634> c<632> l<27:9> el<27:42> +n<> u<634> t p<635> c<633> l<27:9> el<27:42> +n<> u<635> t p<713> c<634> s<654> l<27:9> el<27:42> +n u<636> t p<637> l<28:17> el<28:28> +n<> u<637> t p<638> c<636> l<28:17> el<28:28> +n<> u<638> t p<639> c<637> l<28:17> el<28:28> +n<> u<639> t p<645> c<638> s<644> l<28:17> el<28:28> +n<4'b1011> u<640> t p<641> l<28:32> el<28:39> +n<> u<641> t p<642> c<640> l<28:32> el<28:39> +n<> u<642> t p<643> c<641> l<28:32> el<28:39> +n<> u<643> t p<645> c<642> l<28:32> el<28:39> +n<> u<644> t p<645> s<643> l<28:29> el<28:31> +n<> u<645> t p<648> c<639> s<647> l<28:17> el<28:39> +n<> u<646> t p<647> l<28:40> el<28:41> +n<> u<647> t p<648> c<646> l<28:40> el<28:41> +n<> u<648> t p<649> c<645> l<28:9> el<28:41> +n<> u<649> t p<650> c<648> l<28:9> el<28:41> +n<> u<650> t p<651> c<649> l<28:9> el<28:41> +n<> u<651> t p<652> c<650> l<28:9> el<28:41> +n<> u<652> t p<653> c<651> l<28:9> el<28:41> +n<> u<653> t p<654> c<652> l<28:9> el<28:41> +n<> u<654> t p<713> c<653> s<673> l<28:9> el<28:41> +n u<655> t p<656> l<30:17> el<30:30> +n<> u<656> t p<657> c<655> l<30:17> el<30:30> +n<> u<657> t p<658> c<656> l<30:17> el<30:30> +n<> u<658> t p<664> c<657> s<663> l<30:17> el<30:30> +n<4'b1001> u<659> t p<660> l<30:34> el<30:41> +n<> u<660> t p<661> c<659> l<30:34> el<30:41> +n<> u<661> t p<662> c<660> l<30:34> el<30:41> +n<> u<662> t p<664> c<661> l<30:34> el<30:41> +n<> u<663> t p<664> s<662> l<30:31> el<30:33> +n<> u<664> t p<667> c<658> s<666> l<30:17> el<30:41> +n<> u<665> t p<666> l<30:42> el<30:43> +n<> u<666> t p<667> c<665> l<30:42> el<30:43> +n<> u<667> t p<668> c<664> l<30:9> el<30:43> +n<> u<668> t p<669> c<667> l<30:9> el<30:43> +n<> u<669> t p<670> c<668> l<30:9> el<30:43> +n<> u<670> t p<671> c<669> l<30:9> el<30:43> +n<> u<671> t p<672> c<670> l<30:9> el<30:43> +n<> u<672> t p<673> c<671> l<30:9> el<30:43> +n<> u<673> t p<713> c<672> s<692> l<30:9> el<30:43> +n u<674> t p<675> l<31:17> el<31:30> +n<> u<675> t p<676> c<674> l<31:17> el<31:30> +n<> u<676> t p<677> c<675> l<31:17> el<31:30> +n<> u<677> t p<683> c<676> s<682> l<31:17> el<31:30> +n<4'b1000> u<678> t p<679> l<31:34> el<31:41> +n<> u<679> t p<680> c<678> l<31:34> el<31:41> +n<> u<680> t p<681> c<679> l<31:34> el<31:41> +n<> u<681> t p<683> c<680> l<31:34> el<31:41> +n<> u<682> t p<683> s<681> l<31:31> el<31:33> +n<> u<683> t p<686> c<677> s<685> l<31:17> el<31:41> +n<> u<684> t p<685> l<31:42> el<31:43> +n<> u<685> t p<686> c<684> l<31:42> el<31:43> +n<> u<686> t p<687> c<683> l<31:9> el<31:43> +n<> u<687> t p<688> c<686> l<31:9> el<31:43> +n<> u<688> t p<689> c<687> l<31:9> el<31:43> +n<> u<689> t p<690> c<688> l<31:9> el<31:43> +n<> u<690> t p<691> c<689> l<31:9> el<31:43> +n<> u<691> t p<692> c<690> l<31:9> el<31:43> +n<> u<692> t p<713> c<691> s<711> l<31:9> el<31:43> +n u<693> t p<694> l<32:17> el<32:29> +n<> u<694> t p<695> c<693> l<32:17> el<32:29> +n<> u<695> t p<696> c<694> l<32:17> el<32:29> +n<> u<696> t p<702> c<695> s<701> l<32:17> el<32:29> +n<4'b1011> u<697> t p<698> l<32:33> el<32:40> +n<> u<698> t p<699> c<697> l<32:33> el<32:40> +n<> u<699> t p<700> c<698> l<32:33> el<32:40> +n<> u<700> t p<702> c<699> l<32:33> el<32:40> +n<> u<701> t p<702> s<700> l<32:30> el<32:32> +n<> u<702> t p<705> c<696> s<704> l<32:17> el<32:40> +n<> u<703> t p<704> l<32:41> el<32:42> +n<> u<704> t p<705> c<703> l<32:41> el<32:42> +n<> u<705> t p<706> c<702> l<32:9> el<32:42> +n<> u<706> t p<707> c<705> l<32:9> el<32:42> +n<> u<707> t p<708> c<706> l<32:9> el<32:42> +n<> u<708> t p<709> c<707> l<32:9> el<32:42> +n<> u<709> t p<710> c<708> l<32:9> el<32:42> +n<> u<710> t p<711> c<709> l<32:9> el<32:42> +n<> u<711> t p<713> c<710> s<712> l<32:9> el<32:42> +n<> u<712> t p<713> l<33:5> el<33:8> +n<> u<713> t p<714> c<502> l<18:15> el<33:8> +n<> u<714> t p<715> c<713> l<18:15> el<33:8> +n<> u<715> t p<716> c<714> l<18:15> el<33:8> +n<> u<716> t p<717> c<715> l<18:15> el<33:8> +n<> u<717> t p<718> c<483> l<18:12> el<33:8> +n<> u<718> t p<719> c<717> l<18:12> el<33:8> +n<> u<719> t p<720> c<718> l<18:12> el<33:8> +n<> u<720> t p<721> c<481> l<18:5> el<33:8> +n<> u<721> t p<722> c<720> l<18:5> el<33:8> +n<> u<722> t p<723> c<721> l<18:5> el<33:8> +n<> u<723> t p<725> c<722> s<724> l<18:5> el<33:8> +n<> u<724> t p<725> l<34:1> el<34:10> +n<> u<725> t p<726> c<4> l<1:1> el<34:10> +n<> u<726> t p<727> c<725> l<1:1> el<34:10> +n<> u<727> t p<728> c<726> l<1:1> el<34:10> +n<> u<728> t c<1> l<1:1> el<35:1> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/WireType/dut.sv:1:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/WireType/dut.sv:1:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/WireType/dut.sv:1:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 0. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +always 1 +begin 1 +constant 78 +cont_assign 40 +design 1 +event_control 1 +immediate_assert 12 +integer_typespec 6 +logic_net 24 +logic_typespec 19 +module_inst 3 +operation 12 +packed_array_typespec 1 +range 8 +ref_obj 52 +ref_typespec 30 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +always 2 +begin 2 +constant 78 +cont_assign 60 +design 1 +event_control 2 +immediate_assert 24 +integer_typespec 6 +logic_net 24 +logic_typespec 19 +module_inst 3 +operation 24 +packed_array_typespec 1 +range 8 +ref_obj 84 +ref_typespec 30 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/WireType/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/WireType/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/WireType/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiTypedef: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:typename + |vpiInstance: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRange: + \_range: , line:13:19, endln:13:24 + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiLeftRange: + \_constant: , line:13:20, endln:13:21 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:22, endln:13:23 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiDefName:work@top + |vpiNet: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_logic_0) + |vpiParent: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_typespec: , line:2:10, endln:2:15 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_logic_1) + |vpiParent: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_typespec: , line:3:10, endln:3:15 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_logic_0) + |vpiParent: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_typespec: , line:4:10, endln:4:15 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_logic_1) + |vpiParent: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_typespec: , line:5:10, endln:5:15 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_logic_0) + |vpiParent: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_typespec: , line:6:9, endln:6:14 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiNetType:3 + |vpiNet: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_logic_1) + |vpiParent: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_typespec: , line:7:9, endln:7:14 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiNetType:3 + |vpiNet: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_integer) + |vpiParent: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiFullName:work@top.wire_integer + |vpiActual: + \_integer_typespec: , line:9:10, endln:9:17 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiNet: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_integer) + |vpiParent: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiFullName:work@top.wand_integer + |vpiActual: + \_integer_typespec: , line:10:10, endln:10:17 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiNet: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_integer) + |vpiParent: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiFullName:work@top.wor_integer + |vpiActual: + \_integer_typespec: , line:11:9, endln:11:16 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiNet: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_typename) + |vpiParent: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiNetType:36 + |vpiNet: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_typename) + |vpiParent: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiNetType:36 + |vpiNet: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_typename) + |vpiParent: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiNetType:36 + |vpiProcess: + \_always: , line:18:5, endln:33:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiStmt: + \_event_control: , line:18:12, endln:18:14 + |vpiParent: + \_always: , line:18:5, endln:33:8 + |vpiStmt: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiParent: + \_event_control: , line:18:12, endln:18:14 + |vpiFullName:work@top + |vpiStmt: + \_immediate_assert: , line:19:9, endln:19:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:19:17, endln:19:34 + |vpiParent: + \_immediate_assert: , line:19:9, endln:19:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_logic_0), line:19:17, endln:19:29 + |vpiParent: + \_operation: , line:19:17, endln:19:34 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiOperand: + \_constant: , line:19:33, endln:19:34 + |vpiParent: + \_operation: , line:19:17, endln:19:34 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:20:9, endln:20:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:20:17, endln:20:34 + |vpiParent: + \_immediate_assert: , line:20:9, endln:20:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_logic_1), line:20:17, endln:20:29 + |vpiParent: + \_operation: , line:20:17, endln:20:34 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiOperand: + \_constant: , line:20:33, endln:20:34 + |vpiParent: + \_operation: , line:20:17, endln:20:34 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:21:9, endln:21:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:21:17, endln:21:34 + |vpiParent: + \_immediate_assert: , line:21:9, endln:21:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_logic_0), line:21:17, endln:21:29 + |vpiParent: + \_operation: , line:21:17, endln:21:34 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiOperand: + \_constant: , line:21:33, endln:21:34 + |vpiParent: + \_operation: , line:21:17, endln:21:34 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:22:9, endln:22:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:22:17, endln:22:34 + |vpiParent: + \_immediate_assert: , line:22:9, endln:22:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_logic_1), line:22:17, endln:22:29 + |vpiParent: + \_operation: , line:22:17, endln:22:34 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiOperand: + \_constant: , line:22:33, endln:22:34 + |vpiParent: + \_operation: , line:22:17, endln:22:34 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:23:9, endln:23:35 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:23:17, endln:23:33 + |vpiParent: + \_immediate_assert: , line:23:9, endln:23:35 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_logic_0), line:23:17, endln:23:28 + |vpiParent: + \_operation: , line:23:17, endln:23:33 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiOperand: + \_constant: , line:23:32, endln:23:33 + |vpiParent: + \_operation: , line:23:17, endln:23:33 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:24:9, endln:24:35 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:24:17, endln:24:33 + |vpiParent: + \_immediate_assert: , line:24:9, endln:24:35 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_logic_1), line:24:17, endln:24:28 + |vpiParent: + \_operation: , line:24:17, endln:24:33 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiOperand: + \_constant: , line:24:32, endln:24:33 + |vpiParent: + \_operation: , line:24:17, endln:24:33 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiStmt: + \_immediate_assert: , line:26:9, endln:26:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:26:17, endln:26:40 + |vpiParent: + \_immediate_assert: , line:26:9, endln:26:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_integer), line:26:17, endln:26:29 + |vpiParent: + \_operation: , line:26:17, endln:26:40 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiActual: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiOperand: + \_constant: , line:26:33, endln:26:40 + |vpiParent: + \_operation: , line:26:17, endln:26:40 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiStmt: + \_immediate_assert: , line:27:9, endln:27:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:27:17, endln:27:40 + |vpiParent: + \_immediate_assert: , line:27:9, endln:27:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_integer), line:27:17, endln:27:29 + |vpiParent: + \_operation: , line:27:17, endln:27:40 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiOperand: + \_constant: , line:27:33, endln:27:40 + |vpiParent: + \_operation: , line:27:17, endln:27:40 + |vpiDecompile:4'b1000 + |vpiSize:4 + |BIN:1000 + |vpiConstType:3 + |vpiStmt: + \_immediate_assert: , line:28:9, endln:28:41 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:28:17, endln:28:39 + |vpiParent: + \_immediate_assert: , line:28:9, endln:28:41 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_integer), line:28:17, endln:28:28 + |vpiParent: + \_operation: , line:28:17, endln:28:39 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiOperand: + \_constant: , line:28:32, endln:28:39 + |vpiParent: + \_operation: , line:28:17, endln:28:39 + |vpiDecompile:4'b1011 + |vpiSize:4 + |BIN:1011 + |vpiConstType:3 + |vpiStmt: + \_immediate_assert: , line:30:9, endln:30:43 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:30:17, endln:30:41 + |vpiParent: + \_immediate_assert: , line:30:9, endln:30:43 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_typename), line:30:17, endln:30:30 + |vpiParent: + \_operation: , line:30:17, endln:30:41 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiOperand: + \_constant: , line:30:34, endln:30:41 + |vpiParent: + \_operation: , line:30:17, endln:30:41 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiStmt: + \_immediate_assert: , line:31:9, endln:31:43 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:31:17, endln:31:41 + |vpiParent: + \_immediate_assert: , line:31:9, endln:31:43 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_typename), line:31:17, endln:31:30 + |vpiParent: + \_operation: , line:31:17, endln:31:41 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiOperand: + \_constant: , line:31:34, endln:31:41 + |vpiParent: + \_operation: , line:31:17, endln:31:41 + |vpiDecompile:4'b1000 + |vpiSize:4 + |BIN:1000 + |vpiConstType:3 + |vpiStmt: + \_immediate_assert: , line:32:9, endln:32:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:32:17, endln:32:40 + |vpiParent: + \_immediate_assert: , line:32:9, endln:32:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_typename), line:32:17, endln:32:29 + |vpiParent: + \_operation: , line:32:17, endln:32:40 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiOperand: + \_constant: , line:32:33, endln:32:40 + |vpiParent: + \_operation: , line:32:17, endln:32:40 + |vpiDecompile:4'b1011 + |vpiSize:4 + |BIN:1011 + |vpiConstType:3 + |vpiAlwaysType:1 + |vpiContAssign: + \_cont_assign: , line:2:37, endln:2:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:2:52, endln:2:53 + |vpiParent: + \_cont_assign: , line:2:37, endln:2:53 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_0), line:2:37, endln:2:49 + |vpiParent: + \_cont_assign: , line:2:37, endln:2:53 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiContAssign: + \_cont_assign: , line:3:37, endln:3:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:3:52, endln:3:53 + |vpiParent: + \_cont_assign: , line:3:37, endln:3:53 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_1), line:3:37, endln:3:49 + |vpiParent: + \_cont_assign: , line:3:37, endln:3:53 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiContAssign: + \_cont_assign: , line:4:37, endln:4:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:52, endln:4:53 + |vpiParent: + \_cont_assign: , line:4:37, endln:4:53 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:37, endln:4:49 + |vpiParent: + \_cont_assign: , line:4:37, endln:4:53 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiContAssign: + \_cont_assign: , line:4:62, endln:4:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:77, endln:4:78 + |vpiParent: + \_cont_assign: , line:4:62, endln:4:78 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:62, endln:4:74 + |vpiParent: + \_cont_assign: , line:4:62, endln:4:78 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiContAssign: + \_cont_assign: , line:5:37, endln:5:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:52, endln:5:53 + |vpiParent: + \_cont_assign: , line:5:37, endln:5:53 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:37, endln:5:49 + |vpiParent: + \_cont_assign: , line:5:37, endln:5:53 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiContAssign: + \_cont_assign: , line:5:62, endln:5:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:77, endln:5:78 + |vpiParent: + \_cont_assign: , line:5:62, endln:5:78 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:62, endln:5:74 + |vpiParent: + \_cont_assign: , line:5:62, endln:5:78 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiContAssign: + \_cont_assign: , line:6:35, endln:6:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:49, endln:6:50 + |vpiParent: + \_cont_assign: , line:6:35, endln:6:50 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:35, endln:6:46 + |vpiParent: + \_cont_assign: , line:6:35, endln:6:50 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiContAssign: + \_cont_assign: , line:6:59, endln:6:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:73, endln:6:74 + |vpiParent: + \_cont_assign: , line:6:59, endln:6:74 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:59, endln:6:70 + |vpiParent: + \_cont_assign: , line:6:59, endln:6:74 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiContAssign: + \_cont_assign: , line:7:35, endln:7:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:49, endln:7:50 + |vpiParent: + \_cont_assign: , line:7:35, endln:7:50 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:35, endln:7:46 + |vpiParent: + \_cont_assign: , line:7:35, endln:7:50 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiContAssign: + \_cont_assign: , line:7:59, endln:7:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:73, endln:7:74 + |vpiParent: + \_cont_assign: , line:7:59, endln:7:74 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:59, endln:7:70 + |vpiParent: + \_cont_assign: , line:7:59, endln:7:74 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiContAssign: + \_cont_assign: , line:9:39, endln:9:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:9:54, endln:9:61 + |vpiParent: + \_cont_assign: , line:9:39, endln:9:61 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wire_integer), line:9:39, endln:9:51 + |vpiParent: + \_cont_assign: , line:9:39, endln:9:61 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiActual: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiContAssign: + \_cont_assign: , line:10:39, endln:10:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:54, endln:10:61 + |vpiParent: + \_cont_assign: , line:10:39, endln:10:61 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:39, endln:10:51 + |vpiParent: + \_cont_assign: , line:10:39, endln:10:61 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiContAssign: + \_cont_assign: , line:10:70, endln:10:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:85, endln:10:92 + |vpiParent: + \_cont_assign: , line:10:70, endln:10:92 + |vpiDecompile:4'b1010 + |vpiSize:4 + |BIN:1010 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:70, endln:10:82 + |vpiParent: + \_cont_assign: , line:10:70, endln:10:92 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiContAssign: + \_cont_assign: , line:11:37, endln:11:58 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:51, endln:11:58 + |vpiParent: + \_cont_assign: , line:11:37, endln:11:58 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:37, endln:11:48 + |vpiParent: + \_cont_assign: , line:11:37, endln:11:58 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiContAssign: + \_cont_assign: , line:11:67, endln:11:88 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:81, endln:11:88 + |vpiParent: + \_cont_assign: , line:11:67, endln:11:88 + |vpiDecompile:4'b1010 + |vpiSize:4 + |BIN:1010 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:67, endln:11:78 + |vpiParent: + \_cont_assign: , line:11:67, endln:11:88 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiContAssign: + \_cont_assign: , line:14:41, endln:14:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:14:57, endln:14:64 + |vpiParent: + \_cont_assign: , line:14:41, endln:14:64 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wire_typename), line:14:41, endln:14:54 + |vpiParent: + \_cont_assign: , line:14:41, endln:14:64 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiContAssign: + \_cont_assign: , line:15:41, endln:15:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:57, endln:15:64 + |vpiParent: + \_cont_assign: , line:15:41, endln:15:64 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:41, endln:15:54 + |vpiParent: + \_cont_assign: , line:15:41, endln:15:64 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiContAssign: + \_cont_assign: , line:15:73, endln:15:96 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:89, endln:15:96 + |vpiParent: + \_cont_assign: , line:15:73, endln:15:96 + |vpiDecompile:4'b1010 + |vpiSize:4 + |BIN:1010 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:73, endln:15:86 + |vpiParent: + \_cont_assign: , line:15:73, endln:15:96 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiContAssign: + \_cont_assign: , line:16:39, endln:16:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:54, endln:16:61 + |vpiParent: + \_cont_assign: , line:16:39, endln:16:61 + |vpiDecompile:4'b1001 + |vpiSize:4 + |BIN:1001 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:39, endln:16:51 + |vpiParent: + \_cont_assign: , line:16:39, endln:16:61 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiContAssign: + \_cont_assign: , line:16:70, endln:16:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:85, endln:16:92 + |vpiParent: + \_cont_assign: , line:16:70, endln:16:92 + |vpiDecompile:4'b1010 + |vpiSize:4 + |BIN:1010 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:70, endln:16:82 + |vpiParent: + \_cont_assign: , line:16:70, endln:16:92 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiParent: + \_design: (work@top) + |vpiName:work@top + |vpiTypedef: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiDefName:work@top + |vpiTop:1 + |vpiNet: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_logic_0) + |vpiParent: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_typespec: , line:2:10, endln:2:15 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_logic_1) + |vpiParent: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_typespec: , line:3:10, endln:3:15 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_logic_0) + |vpiParent: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_typespec: , line:4:10, endln:4:15 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_logic_1) + |vpiParent: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_typespec: , line:5:10, endln:5:15 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_logic_0) + |vpiParent: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_typespec: , line:6:9, endln:6:14 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiNetType:3 + |vpiNet: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_logic_1) + |vpiParent: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_typespec: , line:7:9, endln:7:14 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiNetType:3 + |vpiNet: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_integer) + |vpiParent: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiFullName:work@top.wire_integer + |vpiActual: + \_integer_typespec: , line:9:10, endln:9:17 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_integer) + |vpiParent: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiFullName:work@top.wand_integer + |vpiActual: + \_integer_typespec: , line:10:10, endln:10:17 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_integer) + |vpiParent: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiFullName:work@top.wor_integer + |vpiActual: + \_integer_typespec: , line:11:9, endln:11:16 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiNetType:3 + |vpiNet: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wire_typename) + |vpiParent: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wand_typename) + |vpiParent: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiNetType:2 + |vpiNet: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiTypespec: + \_ref_typespec: (work@top.wor_typename) + |vpiParent: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiNetType:3 + |vpiTopModule:1 + |vpiProcess: + \_always: , line:18:5, endln:33:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiStmt: + \_event_control: , line:18:12, endln:18:14 + |vpiParent: + \_always: , line:18:5, endln:33:8 + |vpiStmt: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiParent: + \_event_control: , line:18:12, endln:18:14 + |vpiFullName:work@top + |vpiStmt: + \_immediate_assert: , line:19:9, endln:19:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:19:17, endln:19:34 + |vpiParent: + \_immediate_assert: , line:19:9, endln:19:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_logic_0), line:19:17, endln:19:29 + |vpiParent: + \_operation: , line:19:17, endln:19:34 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiOperand: + \_constant: , line:19:33, endln:19:34 + |vpiStmt: + \_immediate_assert: , line:20:9, endln:20:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:20:17, endln:20:34 + |vpiParent: + \_immediate_assert: , line:20:9, endln:20:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_logic_1), line:20:17, endln:20:29 + |vpiParent: + \_operation: , line:20:17, endln:20:34 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiOperand: + \_constant: , line:20:33, endln:20:34 + |vpiStmt: + \_immediate_assert: , line:21:9, endln:21:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:21:17, endln:21:34 + |vpiParent: + \_immediate_assert: , line:21:9, endln:21:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_logic_0), line:21:17, endln:21:29 + |vpiParent: + \_operation: , line:21:17, endln:21:34 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiOperand: + \_constant: , line:21:33, endln:21:34 + |vpiStmt: + \_immediate_assert: , line:22:9, endln:22:36 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:22:17, endln:22:34 + |vpiParent: + \_immediate_assert: , line:22:9, endln:22:36 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_logic_1), line:22:17, endln:22:29 + |vpiParent: + \_operation: , line:22:17, endln:22:34 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiOperand: + \_constant: , line:22:33, endln:22:34 + |vpiStmt: + \_immediate_assert: , line:23:9, endln:23:35 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:23:17, endln:23:33 + |vpiParent: + \_immediate_assert: , line:23:9, endln:23:35 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_logic_0), line:23:17, endln:23:28 + |vpiParent: + \_operation: , line:23:17, endln:23:33 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiOperand: + \_constant: , line:23:32, endln:23:33 + |vpiStmt: + \_immediate_assert: , line:24:9, endln:24:35 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:24:17, endln:24:33 + |vpiParent: + \_immediate_assert: , line:24:9, endln:24:35 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_logic_1), line:24:17, endln:24:28 + |vpiParent: + \_operation: , line:24:17, endln:24:33 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiOperand: + \_constant: , line:24:32, endln:24:33 + |vpiStmt: + \_immediate_assert: , line:26:9, endln:26:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:26:17, endln:26:40 + |vpiParent: + \_immediate_assert: , line:26:9, endln:26:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_integer), line:26:17, endln:26:29 + |vpiParent: + \_operation: , line:26:17, endln:26:40 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiActual: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiOperand: + \_constant: , line:26:33, endln:26:40 + |vpiStmt: + \_immediate_assert: , line:27:9, endln:27:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:27:17, endln:27:40 + |vpiParent: + \_immediate_assert: , line:27:9, endln:27:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_integer), line:27:17, endln:27:29 + |vpiParent: + \_operation: , line:27:17, endln:27:40 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiOperand: + \_constant: , line:27:33, endln:27:40 + |vpiStmt: + \_immediate_assert: , line:28:9, endln:28:41 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:28:17, endln:28:39 + |vpiParent: + \_immediate_assert: , line:28:9, endln:28:41 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_integer), line:28:17, endln:28:28 + |vpiParent: + \_operation: , line:28:17, endln:28:39 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiOperand: + \_constant: , line:28:32, endln:28:39 + |vpiStmt: + \_immediate_assert: , line:30:9, endln:30:43 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:30:17, endln:30:41 + |vpiParent: + \_immediate_assert: , line:30:9, endln:30:43 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wire_typename), line:30:17, endln:30:30 + |vpiParent: + \_operation: , line:30:17, endln:30:41 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiOperand: + \_constant: , line:30:34, endln:30:41 + |vpiStmt: + \_immediate_assert: , line:31:9, endln:31:43 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:31:17, endln:31:41 + |vpiParent: + \_immediate_assert: , line:31:9, endln:31:43 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wand_typename), line:31:17, endln:31:30 + |vpiParent: + \_operation: , line:31:17, endln:31:41 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiOperand: + \_constant: , line:31:34, endln:31:41 + |vpiStmt: + \_immediate_assert: , line:32:9, endln:32:42 + |vpiParent: + \_begin: (work@top), line:18:15, endln:33:8 + |vpiExpr: + \_operation: , line:32:17, endln:32:40 + |vpiParent: + \_immediate_assert: , line:32:9, endln:32:42 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@top.wor_typename), line:32:17, endln:32:29 + |vpiParent: + \_operation: , line:32:17, endln:32:40 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiOperand: + \_constant: , line:32:33, endln:32:40 + |vpiAlwaysType:1 + |vpiContAssign: + \_cont_assign: , line:2:37, endln:2:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:2:52, endln:2:53 + |vpiParent: + \_cont_assign: , line:2:37, endln:2:53 + |vpiDecompile:0 + |vpiSize:1 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_0), line:2:37, endln:2:49 + |vpiParent: + \_cont_assign: , line:2:37, endln:2:53 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 + |vpiContAssign: + \_cont_assign: , line:3:37, endln:3:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:3:52, endln:3:53 + |vpiParent: + \_cont_assign: , line:3:37, endln:3:53 + |vpiDecompile:1 + |vpiSize:1 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_1), line:3:37, endln:3:49 + |vpiParent: + \_cont_assign: , line:3:37, endln:3:53 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 + |vpiContAssign: + \_cont_assign: , line:4:37, endln:4:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:52, endln:4:53 + |vpiParent: + \_cont_assign: , line:4:37, endln:4:53 + |vpiDecompile:0 + |vpiSize:1 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:37, endln:4:49 + |vpiParent: + \_cont_assign: , line:4:37, endln:4:53 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiContAssign: + \_cont_assign: , line:4:62, endln:4:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:77, endln:4:78 + |vpiParent: + \_cont_assign: , line:4:62, endln:4:78 + |vpiDecompile:1 + |vpiSize:1 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:62, endln:4:74 + |vpiParent: + \_cont_assign: , line:4:62, endln:4:78 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 + |vpiContAssign: + \_cont_assign: , line:5:37, endln:5:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:52, endln:5:53 + |vpiParent: + \_cont_assign: , line:5:37, endln:5:53 + |vpiDecompile:1 + |vpiSize:1 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:37, endln:5:49 + |vpiParent: + \_cont_assign: , line:5:37, endln:5:53 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiContAssign: + \_cont_assign: , line:5:62, endln:5:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:77, endln:5:78 + |vpiParent: + \_cont_assign: , line:5:62, endln:5:78 + |vpiDecompile:1 + |vpiSize:1 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:62, endln:5:74 + |vpiParent: + \_cont_assign: , line:5:62, endln:5:78 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 + |vpiContAssign: + \_cont_assign: , line:6:35, endln:6:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:49, endln:6:50 + |vpiParent: + \_cont_assign: , line:6:35, endln:6:50 + |vpiDecompile:0 + |vpiSize:1 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:35, endln:6:46 + |vpiParent: + \_cont_assign: , line:6:35, endln:6:50 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiContAssign: + \_cont_assign: , line:6:59, endln:6:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:73, endln:6:74 + |vpiParent: + \_cont_assign: , line:6:59, endln:6:74 + |vpiDecompile:0 + |vpiSize:1 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:59, endln:6:70 + |vpiParent: + \_cont_assign: , line:6:59, endln:6:74 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 + |vpiContAssign: + \_cont_assign: , line:7:35, endln:7:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:49, endln:7:50 + |vpiParent: + \_cont_assign: , line:7:35, endln:7:50 + |vpiDecompile:1 + |vpiSize:1 + |UINT:1 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:35, endln:7:46 + |vpiParent: + \_cont_assign: , line:7:35, endln:7:50 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiContAssign: + \_cont_assign: , line:7:59, endln:7:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:73, endln:7:74 + |vpiParent: + \_cont_assign: , line:7:59, endln:7:74 + |vpiDecompile:0 + |vpiSize:1 + |UINT:0 + |vpiConstType:9 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:59, endln:7:70 + |vpiParent: + \_cont_assign: , line:7:59, endln:7:74 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 + |vpiContAssign: + \_cont_assign: , line:9:39, endln:9:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:9:54, endln:9:61 + |vpiLhs: + \_ref_obj: (work@top.wire_integer), line:9:39, endln:9:51 + |vpiParent: + \_cont_assign: , line:9:39, endln:9:61 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiActual: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 + |vpiContAssign: + \_cont_assign: , line:10:39, endln:10:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:54, endln:10:61 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:39, endln:10:51 + |vpiParent: + \_cont_assign: , line:10:39, endln:10:61 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiContAssign: + \_cont_assign: , line:10:70, endln:10:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:85, endln:10:92 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:70, endln:10:82 + |vpiParent: + \_cont_assign: , line:10:70, endln:10:92 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 + |vpiContAssign: + \_cont_assign: , line:11:37, endln:11:58 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:51, endln:11:58 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:37, endln:11:48 + |vpiParent: + \_cont_assign: , line:11:37, endln:11:58 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiContAssign: + \_cont_assign: , line:11:67, endln:11:88 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:81, endln:11:88 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:67, endln:11:78 + |vpiParent: + \_cont_assign: , line:11:67, endln:11:88 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 + |vpiContAssign: + \_cont_assign: , line:14:41, endln:14:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:14:57, endln:14:64 + |vpiLhs: + \_ref_obj: (work@top.wire_typename), line:14:41, endln:14:54 + |vpiParent: + \_cont_assign: , line:14:41, endln:14:64 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 + |vpiContAssign: + \_cont_assign: , line:15:41, endln:15:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:57, endln:15:64 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:41, endln:15:54 + |vpiParent: + \_cont_assign: , line:15:41, endln:15:64 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiContAssign: + \_cont_assign: , line:15:73, endln:15:96 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:89, endln:15:96 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:73, endln:15:86 + |vpiParent: + \_cont_assign: , line:15:73, endln:15:96 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 + |vpiContAssign: + \_cont_assign: , line:16:39, endln:16:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:54, endln:16:61 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:39, endln:16:51 + |vpiParent: + \_cont_assign: , line:16:39, endln:16:61 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 + |vpiContAssign: + \_cont_assign: , line:16:70, endln:16:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:85, endln:16:92 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:70, endln:16:82 + |vpiParent: + \_cont_assign: , line:16:70, endln:16:92 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 +\_weaklyReferenced: +\_logic_typespec: , line:2:10, endln:2:15 +\_logic_typespec: , line:3:10, endln:3:15 +\_logic_typespec: , line:4:10, endln:4:15 +\_logic_typespec: , line:5:10, endln:5:15 +\_logic_typespec: , line:6:9, endln:6:14 +\_logic_typespec: , line:7:9, endln:7:14 +\_integer_typespec: , line:9:10, endln:9:17 + |vpiSigned:1 +\_integer_typespec: , line:10:10, endln:10:17 + |vpiSigned:1 +\_integer_typespec: , line:11:9, endln:11:16 + |vpiSigned:1 +\_logic_typespec: , line:2:10, endln:2:15 +\_logic_typespec: , line:3:10, endln:3:15 +\_logic_typespec: , line:4:10, endln:4:15 +\_logic_typespec: , line:5:10, endln:5:15 +\_logic_typespec: , line:6:9, endln:6:14 +\_logic_typespec: , line:7:9, endln:7:14 +\_integer_typespec: , line:9:10, endln:9:17 + |vpiSigned:1 +\_integer_typespec: , line:10:10, endln:10:17 + |vpiSigned:1 +\_integer_typespec: , line:11:9, endln:11:16 + |vpiSigned:1 +\_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:typename + |vpiTypedefAlias: + \_ref_typespec: (typename) + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiFullName:typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiInstance: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRange: + \_range: , line:13:19, endln:13:24 + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiLeftRange: + \_constant: , line:13:20, endln:13:21 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:22, endln:13:23 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:typename + |vpiTypedefAlias: + \_ref_typespec: (typename) + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiFullName:typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiInstance: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRange: + \_range: , line:13:19, endln:13:24 + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiLeftRange: + \_constant: , line:13:20, endln:13:21 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:22, endln:13:23 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiName:typename + |vpiTypedefAlias: + \_ref_typespec: (typename) + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiFullName:typename + |vpiActual: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiInstance: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRange: + \_range: , line:13:19, endln:13:24 + |vpiParent: + \_logic_typespec: (typename), line:13:13, endln:13:24 + |vpiLeftRange: + \_constant: , line:13:20, endln:13:21 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:13:22, endln:13:23 + |vpiParent: + \_range: , line:13:19, endln:13:24 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_cont_assign: , line:2:37, endln:2:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:2:52, endln:2:53 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_0), line:2:37, endln:2:49 + |vpiParent: + \_cont_assign: , line:2:37, endln:2:53 + |vpiName:wire_logic_0 + |vpiFullName:work@top.wire_logic_0 + |vpiActual: + \_logic_net: (work@top.wire_logic_0), line:2:16, endln:2:28 +\_cont_assign: , line:3:37, endln:3:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:3:52, endln:3:53 + |vpiLhs: + \_ref_obj: (work@top.wire_logic_1), line:3:37, endln:3:49 + |vpiParent: + \_cont_assign: , line:3:37, endln:3:53 + |vpiName:wire_logic_1 + |vpiFullName:work@top.wire_logic_1 + |vpiActual: + \_logic_net: (work@top.wire_logic_1), line:3:16, endln:3:28 +\_cont_assign: , line:4:37, endln:4:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:52, endln:4:53 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:37, endln:4:49 + |vpiParent: + \_cont_assign: , line:4:37, endln:4:53 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 +\_cont_assign: , line:4:62, endln:4:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:4:77, endln:4:78 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_0), line:4:62, endln:4:74 + |vpiParent: + \_cont_assign: , line:4:62, endln:4:78 + |vpiName:wand_logic_0 + |vpiFullName:work@top.wand_logic_0 + |vpiActual: + \_logic_net: (work@top.wand_logic_0), line:4:16, endln:4:28 +\_cont_assign: , line:5:37, endln:5:53 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:52, endln:5:53 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:37, endln:5:49 + |vpiParent: + \_cont_assign: , line:5:37, endln:5:53 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 +\_cont_assign: , line:5:62, endln:5:78 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:5:77, endln:5:78 + |vpiLhs: + \_ref_obj: (work@top.wand_logic_1), line:5:62, endln:5:74 + |vpiParent: + \_cont_assign: , line:5:62, endln:5:78 + |vpiName:wand_logic_1 + |vpiFullName:work@top.wand_logic_1 + |vpiActual: + \_logic_net: (work@top.wand_logic_1), line:5:16, endln:5:28 +\_cont_assign: , line:6:35, endln:6:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:49, endln:6:50 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:35, endln:6:46 + |vpiParent: + \_cont_assign: , line:6:35, endln:6:50 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 +\_cont_assign: , line:6:59, endln:6:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:6:73, endln:6:74 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_0), line:6:59, endln:6:70 + |vpiParent: + \_cont_assign: , line:6:59, endln:6:74 + |vpiName:wor_logic_0 + |vpiFullName:work@top.wor_logic_0 + |vpiActual: + \_logic_net: (work@top.wor_logic_0), line:6:15, endln:6:26 +\_cont_assign: , line:7:35, endln:7:50 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:49, endln:7:50 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:35, endln:7:46 + |vpiParent: + \_cont_assign: , line:7:35, endln:7:50 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 +\_cont_assign: , line:7:59, endln:7:74 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:7:73, endln:7:74 + |vpiLhs: + \_ref_obj: (work@top.wor_logic_1), line:7:59, endln:7:70 + |vpiParent: + \_cont_assign: , line:7:59, endln:7:74 + |vpiName:wor_logic_1 + |vpiFullName:work@top.wor_logic_1 + |vpiActual: + \_logic_net: (work@top.wor_logic_1), line:7:15, endln:7:26 +\_cont_assign: , line:9:39, endln:9:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:9:54, endln:9:61 + |vpiLhs: + \_ref_obj: (work@top.wire_integer), line:9:39, endln:9:51 + |vpiParent: + \_cont_assign: , line:9:39, endln:9:61 + |vpiName:wire_integer + |vpiFullName:work@top.wire_integer + |vpiActual: + \_logic_net: (work@top.wire_integer), line:9:18, endln:9:30 +\_cont_assign: , line:10:39, endln:10:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:54, endln:10:61 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:39, endln:10:51 + |vpiParent: + \_cont_assign: , line:10:39, endln:10:61 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 +\_cont_assign: , line:10:70, endln:10:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:10:85, endln:10:92 + |vpiLhs: + \_ref_obj: (work@top.wand_integer), line:10:70, endln:10:82 + |vpiParent: + \_cont_assign: , line:10:70, endln:10:92 + |vpiName:wand_integer + |vpiFullName:work@top.wand_integer + |vpiActual: + \_logic_net: (work@top.wand_integer), line:10:18, endln:10:30 +\_cont_assign: , line:11:37, endln:11:58 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:51, endln:11:58 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:37, endln:11:48 + |vpiParent: + \_cont_assign: , line:11:37, endln:11:58 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 +\_cont_assign: , line:11:67, endln:11:88 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:11:81, endln:11:88 + |vpiLhs: + \_ref_obj: (work@top.wor_integer), line:11:67, endln:11:78 + |vpiParent: + \_cont_assign: , line:11:67, endln:11:88 + |vpiName:wor_integer + |vpiFullName:work@top.wor_integer + |vpiActual: + \_logic_net: (work@top.wor_integer), line:11:17, endln:11:28 +\_cont_assign: , line:14:41, endln:14:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:14:57, endln:14:64 + |vpiLhs: + \_ref_obj: (work@top.wire_typename), line:14:41, endln:14:54 + |vpiParent: + \_cont_assign: , line:14:41, endln:14:64 + |vpiName:wire_typename + |vpiFullName:work@top.wire_typename + |vpiActual: + \_logic_net: (work@top.wire_typename), line:14:19, endln:14:32 +\_cont_assign: , line:15:41, endln:15:64 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:57, endln:15:64 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:41, endln:15:54 + |vpiParent: + \_cont_assign: , line:15:41, endln:15:64 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 +\_cont_assign: , line:15:73, endln:15:96 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:15:89, endln:15:96 + |vpiLhs: + \_ref_obj: (work@top.wand_typename), line:15:73, endln:15:86 + |vpiParent: + \_cont_assign: , line:15:73, endln:15:96 + |vpiName:wand_typename + |vpiFullName:work@top.wand_typename + |vpiActual: + \_logic_net: (work@top.wand_typename), line:15:19, endln:15:32 +\_cont_assign: , line:16:39, endln:16:61 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:54, endln:16:61 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:39, endln:16:51 + |vpiParent: + \_cont_assign: , line:16:39, endln:16:61 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 +\_cont_assign: , line:16:70, endln:16:92 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WireType/dut.sv, line:1:1, endln:34:10 + |vpiRhs: + \_constant: , line:16:85, endln:16:92 + |vpiLhs: + \_ref_obj: (work@top.wor_typename), line:16:70, endln:16:82 + |vpiParent: + \_cont_assign: , line:16:70, endln:16:92 + |vpiName:wor_typename + |vpiFullName:work@top.wor_typename + |vpiActual: + \_logic_net: (work@top.wor_typename), line:16:18, endln:16:30 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/WireType/dut.sv | ${SURELOG_DIR}/build/regression/WireType/roundtrip/dut_000.sv | 13 | 34 | +============================== End RoundTrip Results ============================== diff --git a/tests/WireType/WireType.sl b/tests/WireType/WireType.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/WireType/WireType.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/WireType/dut.sv b/tests/WireType/dut.sv new file mode 100644 index 0000000000..7226a7ee5e --- /dev/null +++ b/tests/WireType/dut.sv @@ -0,0 +1,34 @@ +module top; + wire logic wire_logic_0; assign wire_logic_0 = 0; + wire logic wire_logic_1; assign wire_logic_1 = 1; + wand logic wand_logic_0; assign wand_logic_0 = 0; assign wand_logic_0 = 1; + wand logic wand_logic_1; assign wand_logic_1 = 1; assign wand_logic_1 = 1; + wor logic wor_logic_0; assign wor_logic_0 = 0; assign wor_logic_0 = 0; + wor logic wor_logic_1; assign wor_logic_1 = 1; assign wor_logic_1 = 0; + + wire integer wire_integer; assign wire_integer = 4'b1001; + wand integer wand_integer; assign wand_integer = 4'b1001; assign wand_integer = 4'b1010; + wor integer wor_integer; assign wor_integer = 4'b1001; assign wor_integer = 4'b1010; + + typedef logic [3:0] typename; + wire typename wire_typename; assign wire_typename = 4'b1001; + wand typename wand_typename; assign wand_typename = 4'b1001; assign wand_typename = 4'b1010; + wor typename wor_typename; assign wor_typename = 4'b1001; assign wor_typename = 4'b1010; + + always @* begin + assert (wire_logic_0 == 0); + assert (wire_logic_1 == 1); + assert (wand_logic_0 == 0); + assert (wand_logic_1 == 1); + assert (wor_logic_0 == 0); + assert (wor_logic_1 == 1); + + assert (wire_integer == 4'b1001); + assert (wand_integer == 4'b1000); + assert (wor_integer == 4'b1011); + + assert (wire_typename == 4'b1001); + assert (wand_typename == 4'b1000); + assert (wor_typename == 4'b1011); + end +endmodule