From d5b2ce1cf6b767b49fd074c1c40c061956e02b9f Mon Sep 17 00:00:00 2001 From: Daniel Lim Wee Soong Date: Fri, 17 Apr 2020 21:44:59 +0800 Subject: [PATCH] Remove netlistsvg diagram for blackbox modules and add pb_type.xml Signed-off-by: Daniel Lim Wee Soong --- tests/clocks/dff_comb_one_clock/README.rst | 7 +++++-- tests/clocks/dff_one_clock/README.rst | 5 ++++- tests/clocks/dff_two_clocks/README.rst | 5 ++++- tests/clocks/input_attr_clock/README.rst | 9 ++++----- tests/clocks/input_attr_not_clock/README.rst | 11 +++++++++-- tests/clocks/input_named_clk/README.rst | 9 ++++----- tests/clocks/input_named_regex/README.rst | 13 ++++++++----- tests/clocks/multiple_inputs_named_clk/README.rst | 9 ++++----- tests/clocks/multiple_outputs_named_clk/README.rst | 9 ++++----- tests/clocks/output_attr_clock/README.rst | 9 ++++----- tests/clocks/output_named_clk/README.rst | 9 ++++----- 11 files changed, 54 insertions(+), 41 deletions(-) diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst index 0e5240ef..438f419b 100644 --- a/tests/clocks/dff_comb_one_clock/README.rst +++ b/tests/clocks/dff_comb_one_clock/README.rst @@ -8,13 +8,16 @@ The following shows a combinational logic design driven by a clock. `input wire .. verilog-diagram:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v The `is_clock` attribute of the `a` port is set to 1, and the ports `b`, `c` and `d` have their `clock` attribute set to `a`. .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/dff_comb_one_clock/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index 8df0b14f..be7e6ee1 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst @@ -8,13 +8,16 @@ The following shows a simple D-flip flop driven by one clock. `input wire a` sho .. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v As you can see in the generated model, the `is_clock` attribute of the `a` port is set to 1, while the `b` and `c` ports have their `clock` attribute set to `a`. .. literalinclude:: ../../../tests/clocks/dff_one_clock/golden.model.xml :language: xml + :caption: tests/clocks/dff_one_clock/golden.model.xml diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index c670361e..bc64b746 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst @@ -8,13 +8,16 @@ D-Flipflop with two clocks .. verilog-diagram:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v + +| .. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v The `is_clock` attribute of the `c1` and `c2` ports are set to 1, and the ports `a`, `b`, `c`, `o1` and `o2` have their `clock` attribute set to the respective clocks they are driven by. .. literalinclude:: ../../../tests/clocks/dff_two_clocks/golden.model.xml :language: xml + :caption: tests/clocks/dff_two_clocks/golden.model.xml diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index acda36d9..a0f047b7 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst @@ -5,16 +5,15 @@ The following shows that `input wire a` is given the `(* CLOCK *)` attribute. .. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v +| .. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v As such, the `is_clock` attribute of the `a` port is set to 1. .. literalinclude:: ../../../tests/clocks/input_attr_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_attr_clock/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index 5a51c279..2b2e93dd 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst @@ -8,13 +8,20 @@ Force input as regular input by setting the CLOCK attribute .. verilog-diagram:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :type: netlistsvg :module: BLOCK - :caption: tests/clocks/input_attr_not_clock/block.sim.v + +| .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_attr_not_clock/block.sim.v As such, the `is_clock` attribute of the `a` port is not set. .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_attr_not_clock/golden.model.xml + +.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.pb_type.xml + :language: xml + :caption: tests/clocks/input_attr_not_clock/golden.pb_type.xml \ No newline at end of file diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index 7d5bdc1c..e3f85801 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst @@ -5,16 +5,15 @@ An input wire can be set as a clock by assigning `clk` as its name. .. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_named_clk/input_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_named_clk/input_named_clk.sim.v As such, the `is_clock` attribute of the `clk` port is set to 1, without needing to set anything else in the verilog code. .. literalinclude:: ../../../tests/clocks/input_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_named_clk/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index a781d067..ab9982a4 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst @@ -5,16 +5,19 @@ An input wire can be set as a clock by having `clk` in its name (case insensitiv .. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_named_regex/block.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/input_named_regex/block.sim.v +| .. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/input_named_regex/block.sim.v As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1. .. literalinclude:: ../../../tests/clocks/input_named_regex/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/input_named_regex/golden.model.xml + +.. literalinclude:: ../../../tests/clocks/input_named_regex/golden.pb_type.xml + :language: xml + :caption: tests/clocks/input_named_regex/golden.pb_type.xml \ No newline at end of file diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst index e5a73ac7..1e379efc 100644 --- a/tests/clocks/multiple_inputs_named_clk/README.rst +++ b/tests/clocks/multiple_inputs_named_clk/README.rst @@ -5,16 +5,15 @@ Set inputs as clock by name (multiple clock inputs) .. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1. .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/multiple_inputs_named_clk/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index f9d00ec8..20496535 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst @@ -5,16 +5,15 @@ Set outputs as clock by name (multiple clock outputs) .. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1. .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/multiple_outputs_named_clk/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index e0d6ca19..16e75e5a 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst @@ -5,16 +5,15 @@ The following shows that `output wire o` is given the `(* CLOCK *)` attribute. .. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v +| .. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v As such, the `is_clock` attribute of the `o` port is set to 1. .. literalinclude:: ../../../tests/clocks/output_attr_clock/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/output_attr_clock/golden.model.xml \ No newline at end of file diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index cfa3677e..4211904e 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst @@ -5,16 +5,15 @@ An output wire can be set as a clock by assigning `clk` as its name. .. symbolator:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v -.. verilog-diagram:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v - :type: netlistsvg - :module: BLOCK - :caption: tests/clocks/output_named_clk/output_named_clk.sim.v +| .. literalinclude:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v :language: verilog :start-after: */ + :caption: tests/clocks/output_named_clk/output_named_clk.sim.v As such, the `is_clock` attribute of the `clk` output port is set to 1. .. literalinclude:: ../../../tests/clocks/output_named_clk/golden.model.xml - :language: xml \ No newline at end of file + :language: xml + :caption: tests/clocks/output_named_clk/golden.model.xml \ No newline at end of file