- 명령어 집합
- 명령어 주기
- RISC / CISC
Instruction Set (명령어 집합)
mod, instruct, address >> CPU
Instruction Cycle (명령어 주기)
CPU가 명령어를 처리하는 흐름
Controller[Decoder / Instruction Register]
<> Control (w/ Memory)
<> ALU (< Accumulator)
Program Counter
Memory Address Register (MAR)
Memory Buffer Register (MBR)
<> (w/ Memory by MAR MBR)
Addressing Mode
- immediate
CISC / RISC
Clock Cycle: Multi-clock Cycle / Single-clock Cycle
Instruction Length: Variable / Fixed
Number of Instruction: Large / Small
Number of Register: Small / Large
TCP
[Data] - (Header - Header - Header )- ...
OOP와 추상화
- 가상 함수
- 좋은 추상화는 곧 확장 가능성