This crate contains the implementation the hardware components in a 5-stage RISC-V processor. For convenience and
portability, the crate is no_std w/ alloc requirements with no default features enabled.
With no features enabled, this crate serves a VM emulating the rv32i ISA. However, it can be extended with the
following features:
64-bit- Enable the 64-bit RISC-V architecture and accompanying instructions.m- Standard Extension for Integer Multiplication and Division.a- Standard Extension for Atomic Instructionsc- Standard Extension for Compressed Instructions.