Move I2C core to Experimental submodule

Since the I2C core is subject to changes in the near future, we've moved it
to an `Experimental` submodule.

Author: hiddemoll

clash-cores/clash-cores.cabal

@@ -124,13 +124,14 @@ library
   hs-source-dirs: src
 
   exposed-modules:
-    Clash.Cores.I2C
-    Clash.Cores.I2C.BitMaster
-    Clash.Cores.I2C.BitMaster.BusCtrl
-    Clash.Cores.I2C.BitMaster.StateMachine
-    Clash.Cores.I2C.ByteMaster
-    Clash.Cores.I2C.ByteMaster.ShiftRegister
-    Clash.Cores.I2C.Types
+    Clash.Cores.Experimental.I2C
+    Clash.Cores.Experimental.I2C.BitMaster
+    Clash.Cores.Experimental.I2C.BitMaster.BusCtrl
+    Clash.Cores.Experimental.I2C.BitMaster.StateMachine
+    Clash.Cores.Experimental.I2C.ByteMaster
+    Clash.Cores.Experimental.I2C.ByteMaster.ShiftRegister
+    Clash.Cores.Experimental.I2C.Types
+
     Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO
     Clash.Cores.LatticeSemi.ECP5.IO
     Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO
@@ -196,9 +197,9 @@ test-suite unittests
     buildable: False
 
   other-Modules:
-    Test.Cores.I2C
-    Test.Cores.I2C.Config
-    Test.Cores.I2C.Slave
+    Test.Cores.Experimental.I2C
+    Test.Cores.Experimental.I2C.Config
+    Test.Cores.Experimental.I2C.Slave
     Test.Cores.Internal.SampleSPI
     Test.Cores.Internal.Signals
     Test.Cores.SPI

clash-cores/src/Clash/Cores/I2C.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C.hs

@@ -9,16 +9,15 @@
 
 {-# LANGUAGE CPP #-}
 
-module Clash.Cores.I2C
+module Clash.Cores.Experimental.I2C
   ( i2c
-  , i2cTop
-  , Clash.Cores.I2C.ByteMaster.I2COperation(..)
+  , Clash.Cores.Experimental.I2C.ByteMaster.I2COperation(..)
   ) where
 
 import Clash.Prelude hiding (read)
 
-import Clash.Cores.I2C.BitMaster
-import Clash.Cores.I2C.ByteMaster
+import Clash.Cores.Experimental.I2C.BitMaster
+import Clash.Cores.Experimental.I2C.ByteMaster
 
 -- | Core for I2C communication. Returns the output enable signals for SCL en SDA
 -- These signals assume that when they are `high`, they pull down SCL and SDA respectively.

clash-cores/src/Clash/Cores/I2C/BitMaster.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/BitMaster.hs

@@ -7,7 +7,7 @@
 
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module Clash.Cores.I2C.BitMaster
+module Clash.Cores.Experimental.I2C.BitMaster
   ( bitMaster
   , BitMasterI
   , BitMasterO
@@ -20,9 +20,9 @@ import Control.Monad
 import Control.Monad.Trans.State
 import Data.Tuple
 
-import Clash.Cores.I2C.BitMaster.BusCtrl
-import Clash.Cores.I2C.BitMaster.StateMachine
-import Clash.Cores.I2C.Types
+import Clash.Cores.Experimental.I2C.BitMaster.BusCtrl
+import Clash.Cores.Experimental.I2C.BitMaster.StateMachine
+import Clash.Cores.Experimental.I2C.Types
 
 -- | Internal state of the I2C BitMaster.
 data BitMasterS

clash-cores/src/Clash/Cores/I2C/BitMaster/BusCtrl.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/BitMaster/BusCtrl.hs

@@ -7,7 +7,7 @@
 
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module Clash.Cores.I2C.BitMaster.BusCtrl
+module Clash.Cores.Experimental.I2C.BitMaster.BusCtrl
   ( busStatusCtrl
   , BusStatusCtrl(..)
   , busStartState
@@ -18,8 +18,8 @@ import Control.Lens
 import Control.Monad
 import Control.Monad.State
 
-import Clash.Cores.I2C.BitMaster.StateMachine
-import Clash.Cores.I2C.Types
+import Clash.Cores.Experimental.I2C.BitMaster.StateMachine
+import Clash.Cores.Experimental.I2C.Types
 
 -- | Bus status control state.
 data BusStatusCtrl

clash-cores/src/Clash/Cores/I2C/BitMaster/StateMachine.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/BitMaster/StateMachine.hs

@@ -7,14 +7,14 @@
 
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module Clash.Cores.I2C.BitMaster.StateMachine where
+module Clash.Cores.Experimental.I2C.BitMaster.StateMachine where
 
 import Clash.Prelude
 import Control.Lens hiding (Index)
 import Control.Monad
 import Control.Monad.State
 
-import Clash.Cores.I2C.Types
+import Clash.Cores.Experimental.I2C.Types
 
 -- | States for bit-level I2C operations.
 data BitStateMachine

clash-cores/src/Clash/Cores/I2C/ByteMaster.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/ByteMaster.hs

@@ -7,7 +7,7 @@
 
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module Clash.Cores.I2C.ByteMaster
+module Clash.Cores.Experimental.I2C.ByteMaster
   ( byteMaster
   , ByteMasterI
   , ByteMasterO
@@ -21,8 +21,8 @@ import Control.Monad
 import Control.Monad.Trans.State
 import Data.Tuple
 
-import Clash.Cores.I2C.ByteMaster.ShiftRegister
-import Clash.Cores.I2C.Types
+import Clash.Cores.Experimental.I2C.ByteMaster.ShiftRegister
+import Clash.Cores.Experimental.I2C.Types
 import Data.Maybe (fromJust)
 
 data ByteStateMachine = Idle | Active | Start | Read | Write | Ack | Stop
@@ -67,8 +67,8 @@ type ByteMasterO = (Bool,Bool,BitVector 8,BitCtrlSig)
 
 -- | Byte level controller, takes care of correctly executing i2c communication
 -- based on the supplied control signals. It should be instantiated alongside
--- 'Clash.Cores.I2C.BitMaster.bitMaster'. The outgoing 'BitCtrlSig' controls the
--- 'Clash.Cores.I2C.BitMaster.bitMaster. whose 'BitRespSig' should be supplied as last
+-- 'Clash.Cores.Experimental.I2C.BitMaster.bitMaster'. The outgoing 'BitCtrlSig' controls the
+-- 'Clash.Cores.Experimental.I2C.BitMaster.bitMaster. whose 'BitRespSig' should be supplied as last
 -- input.
 byteMaster
   :: KnownDomain dom

clash-cores/src/Clash/Cores/I2C/ByteMaster/ShiftRegister.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/ByteMaster/ShiftRegister.hs

@@ -6,7 +6,7 @@
 -}
 
 {-# LANGUAGE RecordWildCards #-}
-module Clash.Cores.I2C.ByteMaster.ShiftRegister where
+module Clash.Cores.Experimental.I2C.ByteMaster.ShiftRegister where
 
 import Clash.Prelude
 

clash-cores/src/Clash/Cores/I2C/Types.hs renamed to clash-cores/src/Clash/Cores/Experimental/I2C/Types.hs

@@ -5,7 +5,7 @@
   Maintainer  :  QBayLogic B.V. <[email protected]>
 -}
 
-module Clash.Cores.I2C.Types where
+module Clash.Cores.Experimental.I2C.Types where
 
 import Clash.Prelude
 

clash-cores/test/Test/Cores/I2C.hs renamed to clash-cores/test/Test/Cores/Experimental/I2C.hs

@@ -1,15 +1,15 @@
 {-# LANGUAGE CPP #-}
 
-module Test.Cores.I2C where
+module Test.Cores.Experimental.I2C where
 
 import qualified Data.List as L
 
 import Clash.Explicit.Prelude
-import Clash.Cores.I2C
+import Clash.Cores.Experimental.I2C
 
 import Data.Maybe
-import Test.Cores.I2C.Config
-import Test.Cores.I2C.Slave
+import Test.Cores.Experimental.I2C.Config
+import Test.Cores.Experimental.I2C.Slave
 import Test.Tasty
 import Test.Tasty.HUnit
 

clash-cores/test/Test/Cores/I2C/Config.hs renamed to clash-cores/test/Test/Cores/Experimental/I2C/Config.hs

@@ -1,13 +1,13 @@
 {-# LANGUAGE CPP #-}
 
-module Test.Cores.I2C.Config where
+module Test.Cores.Experimental.I2C.Config where
 
 import Clash.Prelude
 import Clash.Explicit.SimIO
 import Control.Monad (when)
 import Numeric (showHex)
 
-import Clash.Cores.I2C.ByteMaster (I2COperation(..))
+import Clash.Cores.Experimental.I2C.ByteMaster (I2COperation(..))
 
 data ConfStateMachine = CONFena  |
                         CONFaddr | CONFaddrAck |

clash-cores/test/Test/Cores/I2C/Slave.hs renamed to clash-cores/test/Test/Cores/Experimental/I2C/Slave.hs

@@ -1,6 +1,6 @@
 {-# LANGUAGE CPP #-}
 
-module Test.Cores.I2C.Slave where
+module Test.Cores.Experimental.I2C.Slave where
 
 import Clash.Prelude
 import Clash.Explicit.SimIO

clash-cores/test/unittests.hs

@@ -10,7 +10,7 @@ module Main where
 import Prelude
 import Test.Tasty
 
-import qualified Test.Cores.I2C
+import qualified Test.Cores.Experimental.I2C
 import qualified Test.Cores.SPI
 import qualified Test.Cores.SPI.MultiSlave
 import qualified Test.Cores.UART
@@ -20,7 +20,7 @@ import qualified Test.Cores.Xilinx.DnaPortE2
 
 tests :: TestTree
 tests = testGroup "Unittests"
-  [ Test.Cores.I2C.i2cTest
+  [ Test.Cores.Experimental.I2C.i2cTest
   , Test.Cores.SPI.tests
   , Test.Cores.SPI.MultiSlave.tests
   , Test.Cores.UART.tests