Make i2c core's domain polymorph

Author: lmbollen

clash-cores/src/Clash/Cores/I2C.hs

@@ -40,30 +40,32 @@ import Clash.Cores.I2C.ByteMaster
     }) #-}
 -- | Core for I2C communication
 i2c ::
+  forall dom .
+  KnownDomain dom =>
   -- | Input Clock
-  Clock System ->
+  Clock dom ->
   -- | Low level reset
-  Reset System ->
+  Reset dom ->
   -- | Statemachine reset
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | BitMaster enable
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Clock divider
-  Signal System (Unsigned 16) ->
+  Signal dom (Unsigned 16) ->
   -- | Start signal
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Stop signal
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Read signal
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Write signal
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Ack signal
-  Signal System Bool ->
+  Signal dom Bool ->
   -- | Input data
-  Signal System (BitVector 8) ->
+  Signal dom (BitVector 8) ->
   -- | I2C input signals (SCL, SDA)
-  Signal System (Bit, Bit) ->
+  Signal dom (Bit, Bit) ->
   -- |
   -- 1. Received data
   -- 2. Command acknowledgement
@@ -75,12 +77,12 @@ i2c ::
   --    6.2 SCL Output enable`
   --    6.3 SDA
   --    6.4 SDA Output enable
-  ( Signal System (BitVector 8)
-  , Signal System Bool
-  , Signal System Bool
-  , Signal System Bool
-  , Signal System Bool
-  , Signal System (Bit, Bool, Bit, Bool))
+  ( Signal dom (BitVector 8)
+  , Signal dom Bool
+  , Signal dom Bool
+  , Signal dom Bool
+  , Signal dom Bool
+  , Signal dom (Bit, Bool, Bit, Bool))
 i2c clk arst rst ena clkCnt start stop read write ackIn din i2cI = (dout,hostAck,busy,al,ackOut,i2cO)
   where
     (hostAck,ackOut,dout,bitCtrl) = byteMaster clk arst enableGen (rst,start,stop,read,write,ackIn,din,bitResp)

clash-cores/src/Clash/Cores/I2C/BitMaster.hs

@@ -81,11 +81,12 @@ type BitMasterO = (BitRespSig,Bool,I2COut)
                      ]
     }) #-}
 bitMaster
-  :: Clock System
-  -> Reset System
-  -> Enable System
-  -> Unbundled System BitMasterI
-  -> Unbundled System BitMasterO
+  :: KnownDomain dom
+  => Clock dom
+  -> Reset dom
+  -> Enable dom
+  -> Unbundled dom BitMasterI
+  -> Unbundled dom BitMasterO
 bitMaster = exposeClockResetEnable (mealyB bitMasterT bitMasterInit)
 -- See: https://github.com/clash-lang/clash-compiler/pull/2511
 {-# CLASH_OPAQUE bitMaster #-}

clash-cores/src/Clash/Cores/I2C/ByteMaster.hs

@@ -76,11 +76,12 @@ type ByteMasterO = (Bool,Bool,BitVector 8,BitCtrlSig)
 -- The outgoing bitCtrl' controls the 'bitMaster' whose 'bitResp' should be supplied
 -- as last input.
 byteMaster
-  :: Clock System
-  -> Reset System
-  -> Enable System
-  -> Unbundled System ByteMasterI
-  -> Unbundled System ByteMasterO
+  :: KnownDomain dom
+  => Clock dom
+  -> Reset dom
+  -> Enable dom
+  -> Unbundled dom ByteMasterI
+  -> Unbundled dom ByteMasterO
 byteMaster = exposeClockResetEnable (mealyB byteMasterT byteMasterInit)
 -- See: https://github.com/clash-lang/clash-compiler/pull/2511
 {-# CLASH_OPAQUE byteMaster #-}