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New: DiffClock (#2529)
A new type is introduced to signify a differential clock signal that is passed to the design on two ports in antiphase. This is used by Xilinx `clockWizardDifferential` (note that Intel solves this case differently, so if we were to add an Intel primitive it would not need this type). With this new type, we prevent the creation of more `create_clock` statements in the global SDC file than is correct: only the positive phase of a differential pair should have a `create_clock` statement. Fixes #2518
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‎changelog/2023-07-05T16_49_21+02_00_diffclock‎

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@@ -0,0 +1,9 @@
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ADDED: A new clock type `DiffClock` is introduced to signify a differential
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clock signal that is passed to the design on two ports in antiphase. This is
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used by the Xilinx `clockWizardDifferential` IP generator.
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CHANGED: Xilinx `clockWizardDifferential` now gets its input clock as a
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`DiffClock` type; use `seClockToDiffClock` to generate this in your test bench
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if needed. Previously, the function received two clock inputs, but this
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generated `create_clock` statements in the top-level SDC file for both phases
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which is incorrect.

‎clash-ghc/src-ghc/Clash/GHC/NetlistTypes.hs‎

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@@ -1,7 +1,7 @@
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{-|
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Copyright : (C) 2013-2016, University of Twente,
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2016-2023, Myrtle Software Ltd,
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2021-2022, QBayLogic B.V.
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2021-2023, QBayLogic B.V.
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License : BSD2 (see the file LICENSE)
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Maintainer : QBayLogic B.V. <[email protected]>
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-}
@@ -185,6 +185,12 @@ ghcTypeToHWType iw = go
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tag1 <- domTag m tag0
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returnN (Clock (pack tag1))
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"Clash.Signal.Internal.ClockN"
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| [tag0] <- args
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-> do
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tag1 <- domTag m tag0
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returnN (ClockN (pack tag1))
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"Clash.Signal.Internal.Reset"
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| [tag0] <- args
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-> do

‎clash-lib/prims/common/Clash_Xilinx_ClockGen.primitives.yaml‎

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@@ -0,0 +1,11 @@
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- BlackBox:
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name: Clash.Xilinx.ClockGen.clockWizardDifferential
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kind: Declaration
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTF
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includes:
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- name: clk_wiz
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extension: clash.tcl
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTclTF
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workInfo: Always

‎clash-lib/prims/commonverilog/Clash_Explicit_Testbench.primitives.yaml‎

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@@ -8,4 +8,4 @@
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- BlackBox:
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name: Clash.Explicit.Testbench.seClockToDiffClock
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kind: Expression
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template: '{~ARG[0], ~ ~ARG[0]}'
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template: '{~ARG[1], ~ ~ARG[1]}'

‎clash-lib/prims/commonverilog/Clash_Xilinx_ClockGen.primitives.yaml‎

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@@ -23,30 +23,3 @@
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardTclTF
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workInfo: Always
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- BlackBox:
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name: Clash.Xilinx.ClockGen.clockWizardDifferential
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kind: Declaration
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type: |-
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clockWizardDifferential
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:: ( KnownDomain domIn -- ARG[0]
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, KnownDomain domOut ) -- ARG[1]
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:: SSymbol name -- ARG[2]
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-> Clock domIn -- ARG[3]
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-> Clock domIn -- ARG[4]
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-> Reset domIn -- ARG[5]
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-> (Clock domOut, Signal domOut Bool)
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template: |-
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// clockWizardDifferential begin
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~NAME[2] ~GENSYM[clockWizardDifferential_inst][2]
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(.clk_in1_n (~ARG[3])
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,.clk_in1_p (~ARG[4])
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,.reset (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[5])
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,.clk_out1 (~RESULT[1])
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,.locked (~RESULT[0]));
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// clockWizardDifferential end
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includes:
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- name: clk_wiz
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extension: clash.tcl
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTclTF
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workInfo: Always

‎clash-lib/prims/vhdl/Clash_Explicit_Testbench.primitives.yaml‎

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@@ -158,4 +158,4 @@
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- BlackBox:
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name: Clash.Explicit.Testbench.seClockToDiffClock
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kind: Expression
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template: (~ARG[0], not ~ARG[0])
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template: (~ARG[1], not ~ARG[1])

‎clash-lib/prims/vhdl/Clash_Xilinx_ClockGen.primitives.yaml‎

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@@ -34,41 +34,3 @@
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardTclTF
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workInfo: Always
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- BlackBox:
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name: Clash.Xilinx.ClockGen.clockWizardDifferential
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kind: Declaration
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type: |-
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clockWizard
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:: ( KnownDomain domIn -- ARG[0]
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, KnownDomain domOut ) -- ARG[1]
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=> SSymbol name -- ARG[2]
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-> Clock domIn -- ARG[3]
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-> Clock domIn -- ARG[4]
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-> Reset domIn -- ARG[5]
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-> (Clock domOut, Signal domOut Bool)
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template: |-
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-- clockWizardDifferential begin
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~GENSYM[clockWizardDifferential][0] : block
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signal ~GENSYM[pllOut][1] : std_logic;
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signal ~GENSYM[locked][2] : std_logic;
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signal ~GENSYM[pllLock][3] : boolean;
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component ~NAME[2]
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port (clk_in1_n : in std_logic;
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clk_in1_p : in std_logic;
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reset : in std_logic;
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clk_out1 : out std_logic;
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locked : out std_logic);
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end component;
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begin
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~GENSYM[clockWizardDifferential_inst][4] : component ~NAME[2]
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port map (~ARG[3],~ARG[4],~IF ~ISACTIVEHIGH[0] ~THEN ~ARG[5] ~ELSE NOT(~ARG[5]) ~FI,~SYM[1],~SYM[2]);
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~SYM[3] <= true when ~SYM[2] = '1' else false;
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~RESULT <= (~SYM[1],~SYM[3]);
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end block;
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-- clockWizardDifferential end
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includes:
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- name: clk_wiz
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extension: clash.tcl
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format: Haskell
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templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTclTF
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workInfo: Always

‎clash-lib/src/Clash/Backend/SystemVerilog.hs‎

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@@ -1,7 +1,7 @@
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{-|
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Copyright : (C) 2015-2016, University of Twente,
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2017-2018, Google Inc.,
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2021-2022, QBayLogic B.V.
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2021-2023, QBayLogic B.V.,
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2022 , Google Inc.
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License : BSD2 (see the file LICENSE)
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Maintainer : QBayLogic B.V. <[email protected]>
@@ -330,6 +330,7 @@ normaliseType ty@(Index _) = return (Unsigned (typeSize ty))
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normaliseType ty@(Sum _ _) = return (BitVector (typeSize ty))
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normaliseType ty@(CustomSum _ _ _ _) = return (BitVector (typeSize ty))
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normaliseType (Clock _) = return Bit
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normaliseType (ClockN _) = return Bit
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normaliseType (Reset _) = return Bit
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normaliseType (Enable _) = return Bool
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normaliseType (BiDirectional dir ty) = BiDirectional dir <$> normaliseType ty
@@ -394,6 +395,7 @@ splitVecTy = fmap splitElemTy . go
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Product {} -> (ns, verilogType t)
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Vector {} -> error $ $(curLoc) ++ "impossible"
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Clock {} -> (ns, verilogType t)
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ClockN {} -> (ns, verilogType t)
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Reset {} -> (ns, "logic")
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Enable {} -> (ns, "logic")
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Bool -> (ns, "logic")
@@ -596,6 +598,7 @@ verilogType t_ = do
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RTree {} -> pvrType
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Signed n -> logicOrWire <+> "signed" <+> brackets (int (n-1) <> colon <> int 0)
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Clock _ -> "logic"
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ClockN _ -> "logic"
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Reset _ -> "logic"
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Enable _ -> "logic"
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Bit -> "logic"
@@ -645,6 +648,7 @@ tyName t@(Product nm _ _) = do
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646649
tyName t@(SP _ _) = "logic_vector_" <> int (typeSize t)
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tyName (Clock _) = "logic"
651+
tyName (ClockN _) = "logic"
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tyName (Reset _) = "logic"
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tyName (Enable _) = "logic"
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tyName t = error $ $(curLoc) ++ "tyName: " ++ show t

‎clash-lib/src/Clash/Backend/VHDL.hs‎

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@@ -177,6 +177,7 @@ instance Backend VHDLState where
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if enums then pure UserType else pure SynonymType
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Clock {} -> pure SynonymType
180+
ClockN {} -> pure SynonymType
180181
Reset {} -> pure SynonymType
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Enable {} -> pure SynonymType
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Index {} -> pure SynonymType
@@ -602,6 +603,7 @@ tyDec hwty = do
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-- Type aliases:
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Clock _ -> typAliasDec hwty
606+
ClockN _ -> typAliasDec hwty
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Reset _ -> typAliasDec hwty
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Enable _ -> typAliasDec hwty
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Index _ -> typAliasDec hwty
@@ -1196,6 +1198,9 @@ tyName' rec0 (filterTransparent -> t) = do
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Clock nm0 ->
11971199
let nm1 = "clk_" `TextS.append` nm0 in
11981200
Ap $ makeCached (t, False) nameCache (userTyName "clk" nm1 t)
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ClockN nm0 ->
1202+
let nm1 = "clk_n_" `TextS.append` nm0 in
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Ap $ makeCached (t, False) nameCache (userTyName "clk" nm1 t)
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Reset nm0 ->
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let nm1 = "rst_" `TextS.append` nm0 in
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Ap $ makeCached (t, False) nameCache (userTyName "rst" nm1 t)
@@ -1248,6 +1253,7 @@ normaliseType enums@(RenderEnums e) hwty = case hwty of
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12491254
-- Simple types, for which a subtype (without qualifiers) will be made in VHDL:
12501255
Clock _ -> Bit
1256+
ClockN _ -> Bit
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Reset _ -> Bit
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Enable _ -> Bool
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Index _ -> Unsigned (typeSize hwty)
@@ -1271,6 +1277,7 @@ filterTransparent hwty = case hwty of
12711277
Integer -> hwty
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Bit -> hwty
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Clock _ -> hwty
1280+
ClockN _ -> hwty
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Reset _ -> hwty
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Enable _ -> hwty
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Index _ -> hwty
@@ -1349,6 +1356,7 @@ sizedQualTyNameErrValue t@(Sum _ _) = do
13491356
else
13501357
qualTyName t <> "'" <> parens (int 0 <+> "to" <+> int (typeSize t - 1) <+> rarrow <+> singularErrValue)
13511358
sizedQualTyNameErrValue (Clock _) = singularErrValue
1359+
sizedQualTyNameErrValue (ClockN _) = singularErrValue
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sizedQualTyNameErrValue (Reset _) = singularErrValue
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sizedQualTyNameErrValue (Enable _) = singularErrValue
13541362
sizedQualTyNameErrValue (Void {}) =
@@ -1948,6 +1956,9 @@ toSLV Bit e = do
19481956
toSLV (Clock {}) e = do
19491957
nm <- Ap $ use modNm
19501958
pretty nm <> "_types.toSLV" <> parens (expr_ False e)
1959+
toSLV (ClockN {}) e = do
1960+
nm <- Ap $ use modNm
1961+
pretty nm <> "_types.toSLV" <> parens (expr_ False e)
19511962
toSLV (Reset {}) e = do
19521963
nm <- Ap $ use modNm
19531964
pretty (TextS.toLower nm) <> "_types.toSLV" <> parens (expr_ False e)
@@ -2034,6 +2045,7 @@ punctuate' s d = vcat (punctuate s d) <> s
20342045

20352046
encodingNote :: HWType -> VHDLM Doc
20362047
encodingNote (Clock _) = "-- clock" <> line
2048+
encodingNote (ClockN _) = "-- clock (neg phase)" <> line
20372049
encodingNote (Reset _) = "-- reset" <> line
20382050
encodingNote (Enable _) = "-- enable" <> line
20392051
encodingNote (Annotated _ t) = encodingNote t

‎clash-lib/src/Clash/Backend/Verilog.hs‎

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@@ -366,6 +366,7 @@ verilogType :: HWType -> VerilogM Doc
366366
verilogType t = case t of
367367
Signed n -> "signed" <+> brackets (int (n-1) <> colon <> int 0)
368368
Clock {} -> emptyDoc
369+
ClockN {} -> emptyDoc
369370
Reset {} -> emptyDoc
370371
Enable {} -> emptyDoc
371372
Bit -> emptyDoc
@@ -1283,6 +1284,7 @@ punctuate' s d = vcat (punctuate s d) <> s
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12841285
encodingNote :: Applicative m => HWType -> m Doc
12851286
encodingNote (Clock _) = string " // clock"
1287+
encodingNote (ClockN _) = string " // clock (neg phase)"
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encodingNote (Reset _) = string " // reset"
12871289
encodingNote (Enable _) = string " // enable"
12881290
encodingNote (Annotated _ t) = encodingNote t

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