Apply partial applicative operators for Eq and Ord-like functions.

Author: lmbollen

clash-prelude/tests/Clash/Tests/BlockRam.hs

@@ -14,7 +14,7 @@ readRam
   :: (HiddenClockResetEnable dom)
   => Signal dom (Unsigned 4)
   -> Signal dom (Unsigned 8)
-readRam addr = mux (register False $ addr .<. 8) ram (pure 0xff)
+readRam addr = mux (register False $ addr .< 8) ram (pure 0xff)
   where
     ram = blockRam1 NoClearOnReset (SNat @8) 0 addr (pure Nothing)
 

clash-prelude/tests/Clash/Tests/Ram.hs

@@ -51,7 +51,7 @@ ram rd we wr din =
 
 maskOobRead :: Ram
 maskOobRead rd we wr din =
-  maybeIsX <$> mux (rd .<. 2) ram0 (pure 4)
+  maybeIsX <$> mux (rd .< 2) ram0 (pure 4)
  where
   ram0 = asyncRam# clockGen clockGen enableGen d2 rd we wr din
 

tests/shouldfail/Verification/NonTemporal.hs

@@ -25,7 +25,7 @@ assertCvResult
 assertCvResult clk rst gen max results = done
  where
   counter = register clk rst gen (minBound :: n) (succ <$> counter)
-  done = hideAssertion results (counter .==. pure maxBound)
+  done = hideAssertion results (counter .== maxBound)
 {-# INLINE assertCvResult #-}
 
 binaryTest

tests/shouldwork/Basic/AES.hs

@@ -89,7 +89,7 @@ aes
     -> Signal dom (BitVector 128)
     -> Signal dom (BitVector 128)
     -> Signal dom (Unsigned 4, Vec 4 (BitVector 32), BitVector 128, Bool)
-aes start key block = bundle (cnt, roundKey, pack <$> roundState, cnt .==. 11)
+aes start key block = bundle (cnt, roundKey, pack <$> roundState, cnt .== 11)
     where
 
     roundKey :: Signal dom (Vec 4 (BitVector 32))

tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs

@@ -156,10 +156,10 @@ fifoVerifier ::
 fifoVerifier clk rst ena actual = done0
  where
   expected = regEn clk rst ena 0 (isJust <$> actual) $ expected + 1
-  samplesDone = expected .>. 100
+  samplesDone = expected .> 100
   stuckCnt :: Signal dom (Index 25000)
   stuckCnt = regEn clk rst ena 0 (not <$> stuck) $ stuckCnt + 1
-  stuck = stuckCnt .==. pure maxBound
+  stuck = stuckCnt .== maxBound
   -- Delay one cycle so assertion definitely triggers before stopping simulation
   done = register clk rst ena False $ samplesDone .||. stuck
   expected0 = liftA2 (<$) expected actual

tests/shouldwork/Issues/T1187/Utils.hs

@@ -26,7 +26,7 @@ debounce _ initial this = regEn initial stable this
   where
     counter = register (0 :: Index (ClockDivider dom ps)) counter'
     counter' = mux (unchanged initial this) counter 0
-    stable = counter' .==. pure maxBound
+    stable = counter' .== maxBound
 
 roundRobin
     :: forall n dom. (KnownNat n, HiddenClockResetEnable dom)

tests/shouldwork/Xilinx/ClockWizard.hs

@@ -40,8 +40,8 @@ testBench ::
 testBench = done
  where
   (o1, o2) = unbundle $ topEntity clkSE clkDiff rst
-  done1 = o1 .==. pure maxBound
-  done2 = o2 .==. pure maxBound
+  done1 = o1 .== maxBound
+  done2 = o2 .== maxBound
   done  = unsafeSynchronizer clockGen clkSE $ fmap endVhdlSim $
             strictAnd <$> done1 <*> done2
   strictAnd !a !b = a && b