Move I2C example files to clash-cores

lmbollen · lmbollen · commit d41c4e9d25b6 · 2023-10-03T11:56:48.000+02:00
diff --git a/clash-cores/clash-cores.cabal b/clash-cores/clash-cores.cabal
@@ -106,29 +106,43 @@ common basic-config
     QuickCheck,
     string-interpolate        ^>= 0.3,
     template-haskell,
+    transformers,
 
 library
   import: basic-config
   hs-source-dirs: src
 
   exposed-modules:
-    Clash.Cores.Xilinx.Internal
+    Clash.Cores.I2C
+    Clash.Cores.I2C.BitMaster
+    Clash.Cores.I2C.BitMaster.BusCtrl
+    Clash.Cores.I2C.BitMaster.StateMachine
+    Clash.Cores.I2C.ByteMaster
+    Clash.Cores.I2C.ByteMaster.ShiftRegister
+    Clash.Cores.I2C.Types
+    Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO
+    Clash.Cores.LatticeSemi.ECP5.IO
+    Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO
+    Clash.Cores.LatticeSemi.ICE40.IO
+    Clash.Cores.SPI
+    Clash.Cores.UART
     Clash.Cores.Xilinx.BlockRam
     Clash.Cores.Xilinx.BlockRam.BlackBoxes
     Clash.Cores.Xilinx.BlockRam.Internal
     Clash.Cores.Xilinx.DcFifo
     Clash.Cores.Xilinx.DcFifo.Internal.BlackBoxes
     Clash.Cores.Xilinx.DcFifo.Internal.Instances
     Clash.Cores.Xilinx.DcFifo.Internal.Types
-    Clash.Cores.Xilinx.Ila
-    Clash.Cores.Xilinx.Ila.Internal
-    Clash.Cores.Xilinx.VIO
-    Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
     Clash.Cores.Xilinx.Floating
     Clash.Cores.Xilinx.Floating.Annotations
     Clash.Cores.Xilinx.Floating.BlackBoxes
     Clash.Cores.Xilinx.Floating.Explicit
     Clash.Cores.Xilinx.Floating.Internal
+    Clash.Cores.Xilinx.Ila
+    Clash.Cores.Xilinx.Ila.Internal
+    Clash.Cores.Xilinx.Internal
+    Clash.Cores.Xilinx.VIO
+    Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
     Clash.Cores.Xilinx.Xpm
     Clash.Cores.Xilinx.Xpm.Cdc
     Clash.Cores.Xilinx.Xpm.Cdc.ArraySingle
@@ -139,12 +153,6 @@ library
     Clash.Cores.Xilinx.Xpm.Cdc.Handshake.Internal
     Clash.Cores.Xilinx.Xpm.Cdc.Single
     Clash.Cores.Xilinx.Xpm.Cdc.Single.Internal
-    Clash.Cores.SPI
-    Clash.Cores.UART
-    Clash.Cores.LatticeSemi.ICE40.IO
-    Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO
-    Clash.Cores.LatticeSemi.ECP5.IO
-    Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO
 
   ghc-options:
     -fexpose-all-unfoldings
@@ -171,6 +179,9 @@ test-suite unittests
     buildable: False
 
   other-Modules:
+    Test.Cores.I2C
+    Test.Cores.I2C.I2CConfig
+    Test.Cores.I2C.I2CSlave
     Test.Cores.Internal.SampleSPI
     Test.Cores.Internal.Signals
     Test.Cores.SPI
diff --git a/clash-cores/src/Clash/Cores/I2C.hs b/clash-cores/src/Clash/Cores/I2C.hs
@@ -1,12 +1,12 @@
 {-# LANGUAGE CPP #-}
 
-module I2C where
+module Clash.Cores.I2C where
 
 import Clash.Prelude
 
-import I2C.BitMaster
-import I2C.ByteMaster
-import I2C.Types
+import Clash.Cores.I2C.BitMaster
+import Clash.Cores.I2C.ByteMaster
+import Clash.Cores.I2C.Types
 
 {-# ANN i2c
   (Synthesize
diff --git a/clash-cores/src/Clash/Cores/I2C/BitMaster.hs b/clash-cores/src/Clash/Cores/I2C/BitMaster.hs
@@ -1,6 +1,6 @@
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module I2C.BitMaster (bitMaster) where
+module Clash.Cores.I2C.BitMaster (bitMaster) where
 
 import Clash.Prelude
 
@@ -9,9 +9,9 @@ import Control.Monad
 import Control.Monad.Trans.State
 import Data.Tuple
 
-import I2C.BitMaster.BusCtrl
-import I2C.BitMaster.StateMachine
-import I2C.Types
+import Clash.Cores.I2C.BitMaster.BusCtrl
+import Clash.Cores.I2C.BitMaster.StateMachine
+import Clash.Cores.I2C.Types
 
 data BitMasterS
   = BitS
diff --git a/clash-cores/src/Clash/Cores/I2C/BitMaster/BusCtrl.hs b/clash-cores/src/Clash/Cores/I2C/BitMaster/BusCtrl.hs
@@ -1,14 +1,14 @@
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module I2C.BitMaster.BusCtrl where
+module Clash.Cores.I2C.BitMaster.BusCtrl where
 
 import Clash.Prelude
 import Control.Lens
 import Control.Monad
 import Control.Monad.State
 
-import I2C.BitMaster.StateMachine
-import I2C.Types
+import Clash.Cores.I2C.BitMaster.StateMachine
+import Clash.Cores.I2C.Types
 
 data BusStatusCtrl
   = BusStatusCtrl
diff --git a/clash-cores/src/Clash/Cores/I2C/BitMaster/StateMachine.hs b/clash-cores/src/Clash/Cores/I2C/BitMaster/StateMachine.hs
@@ -1,13 +1,13 @@
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module I2C.BitMaster.StateMachine where
+module Clash.Cores.I2C.BitMaster.StateMachine where
 
 import Clash.Prelude
 import Control.Lens hiding (Index)
 import Control.Monad
 import Control.Monad.State
 
-import I2C.Types
+import Clash.Cores.I2C.Types
 
 data BitStateMachine
   = Idle
diff --git a/clash-cores/src/Clash/Cores/I2C/ByteMaster.hs b/clash-cores/src/Clash/Cores/I2C/ByteMaster.hs
@@ -1,6 +1,6 @@
 {-# LANGUAGE CPP #-}
 {-# LANGUAGE RecordWildCards #-}
-module I2C.ByteMaster (byteMaster) where
+module Clash.Cores.I2C.ByteMaster (byteMaster) where
 
 import Clash.Prelude
 
@@ -9,8 +9,8 @@ import Control.Monad
 import Control.Monad.Trans.State
 import Data.Tuple
 
-import I2C.ByteMaster.ShiftRegister
-import I2C.Types
+import Clash.Cores.I2C.ByteMaster.ShiftRegister
+import Clash.Cores.I2C.Types
 
 data ByteStateMachine = Idle | Start | Read | Write | Ack | Stop
   deriving (Show, Generic, NFDataX)
diff --git a/clash-cores/src/Clash/Cores/I2C/ByteMaster/ShiftRegister.hs b/clash-cores/src/Clash/Cores/I2C/ByteMaster/ShiftRegister.hs
@@ -1,5 +1,5 @@
 {-# LANGUAGE RecordWildCards #-}
-module I2C.ByteMaster.ShiftRegister where
+module Clash.Cores.I2C.ByteMaster.ShiftRegister where
 
 import Clash.Prelude
 
diff --git a/clash-cores/src/Clash/Cores/I2C/Types.hs b/clash-cores/src/Clash/Cores/I2C/Types.hs
@@ -1,4 +1,4 @@
-module I2C.Types where
+module Clash.Cores.I2C.Types where
 
 import Clash.Prelude
 
diff --git a/clash-cores/test/Test/Cores/I2C.hs b/clash-cores/test/Test/Cores/I2C.hs
@@ -1,14 +1,14 @@
 {-# LANGUAGE CPP #-}
 
-module I2Ctest where
+module Test.Cores.I2C where
 
 import qualified Data.List as L
 
 import Clash.Explicit.Prelude
-import I2C
+import Clash.Cores.I2C
 
-import I2Ctest.I2CSlave
-import I2Ctest.I2CConfig
+import Test.Cores.I2C.I2CSlave
+import Test.Cores.I2C.I2CConfig
 
 system0 :: Clock System -> Reset System -> Signal System (Vec 16 (Unsigned 8), Bool, Bool)
 system0 clk arst = bundle (regFile,done,fault)
diff --git a/clash-cores/test/Test/Cores/I2C/I2CConfig.hs b/clash-cores/test/Test/Cores/I2C/I2CConfig.hs
@@ -1,6 +1,6 @@
 {-# LANGUAGE CPP #-}
 
-module I2Ctest.I2CConfig where
+module Test.Cores.I2C.I2CConfig where
 
 import Clash.Prelude
 import Clash.Explicit.SimIO
diff --git a/clash-cores/test/Test/Cores/I2C/I2CSlave.hs b/clash-cores/test/Test/Cores/I2C/I2CSlave.hs
@@ -1,6 +1,6 @@
 {-# LANGUAGE CPP #-}
 
-module I2Ctest.I2CSlave where
+module Test.Cores.I2C.I2CSlave where
 
 import Clash.Prelude
 import Clash.Explicit.SimIO

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module I2C.Types where`
	`1`	`+module Clash.Cores.I2C.Types where`
`2`	`2`
`3`	`3`	`import Clash.Prelude`
`4`	`4`