Superfluous port names in a `Synthesize` annotation get silently ignored

[martijnbastiaan]

Superfluous port names in a Synthesize annotation get silently ignored. This is true for both inputs and outputs:

module Test where
  
import Clash.Prelude

{-# ANN topEntity
  (Synthesize
    { t_name     = "test"
    , t_inputs   = 
      [ PortProduct "" 
        [ PortName "i_a"
        , PortName "i_b"
        , PortName "i_c"
        ]
      ]
    , t_output  = PortProduct "" 
      [ PortName "o_a"
      , PortName "o_b"
      , PortName "o_c"
      ]
}) #-}
topEntity :: (Int, Int) -> (Int, Int)
topEntity (a, c) = (a, c)

Yields:

$ stack run clash -- Test.hs -fclash-no-cache --verilog
GHC: Setting up GHC took: 0.034s
GHC: Compiling and loading modules took: 0.303s
Clash: Parsing and compiling primitives took 0.165s
GHC+Clash: Loading modules cumulatively took 0.627s
Clash: Ignoring previously made caches
Clash: Compiling Test.topEntity
Clash: Normalization took 0.000s
Clash: Netlist generation took 0.000s
Clash: Compiling Test.topEntity took 0.009s
Clash: Total compilation took 0.636s

This can be especially confusing if you deleted one of the middle arguments, causing all port names to shift and up with unexpected names.