Vivado's `mod` misbheaves on negative dividend

[martijnbastiaan]

import Clash.Prelude
import Clash.Explicit.Testbench
import Data.Int (Int8)

topEntity :: (Int8, Int8) -> Int8
topEntity = uncurry mod
{-# NOINLINE topEntity #-}

testBench :: Signal System Bool
testBench = done
  where
    testInput      = stimuliGenerator clk rst ((-1, 3) :> Nil)
    expectedOutput = outputVerifier' clk rst (2 :> Nil)
    done           = expectedOutput (topEntity <$> testInput)
    clk            = tbSystemClockGen (not <$> done)
    rst            = systemResetGen

This fails; Vivado thinks -1 % 3 = 1. The VHDL spec is unambiguous about it:

The result of the modulus operation is such that (A mod B) has the sign of B and an absolute value less than the absolute value of B; in addition, for some integer value N, this result must satisfy the relation:

A = B ∗ N + (A mod B)

This only works if N ~ -1 which in turn implies -1 % 3 = 2.

This issue has been discovered as part of #2257.

[DigitalBrains1]

I made a mistake in the commit message of #2335. I accidentally wrote that #2335 closes this issue, but this is not the case. Please disregard the "commit that referenced this issue" and "DigitalBrains1 mentioned this issue" immediately preceding this comment.