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Verilog generation runs indefinitely #2834

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@kleinreact

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@kleinreact

Clash seems to diverge on the following reproducer (if being called with the --verilog flag).

-- diverges for: Size > 1
type Size = 2

topEntity :: Bit
topEntity = head table

table :: Vec Size Bit
table = lookupTable
 where
  lookupTable :: Vec Size Bit
  lookupTable = smap fill $ repeat ()

  fill :: forall n. SNat n -> () -> Bit
  fill n@(SNat :: SNat n) _ = case compareSNat n (SNat @0) of
    SNatLE -> low
    SNatGT -> case compareSNat n (SNat @Size) of
      SNatLE -> at @(n - 1) @(Size - n) SNat lookupTable
      SNatGT -> error "impossible"

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