`deconstructProduct` shouldn't generate superfluous signals

I'm using `Clash.Primitives.DSL.deconstructProduct` to deconstruct a tuple. This gets me the following HDL:

```verilog
assign product = {CLK_125MHZ_p,   CLK_125MHZ_n};
assign I = product[1:1];
assign IB = product[0:0];
```

Ideally `deconstructProduct` wouldn't generate the intermediate signal `product` if it can see that its argument already consists of 2 `Identifier`s.