lm5066h.txt

LM5066Hx 5.5V to 90V, Advanced Hotswap Controller With I/V/P Monitoring and 
PMBus® Interface
1 Features
•
Input operating voltage range: 5.5V to 90V
–
100V absolute maximum rating
–
Withstands negative voltages up to –5V at 
output
•
Adjustable ILIM thresholds from 10mV to 50mV
•
Programmable FET SOA protection
•
Programmable overcurrent blanking with digital 
timer
•
Strong gate pull down (1.5A) for fast turn OFF
•
Robust short-circuit protection
–
Fast trip response (270ns)
–
Immune to supply line transients
•
LM5066H2 with additional features
–
Dual gate drive for high power applications
–
SYNC pin for parallel controller operation
–
Soft start capacitor disconnect
•
Failed FET detection
•
Programable UV, OV, tFAULT thresholds
•
External FET temperature sensing
•
Failed FET detection
•
PMBus® interface for telemetry, control, 
configuration and debug
–
On chip EEPROM nonvolatile memory for 
configuration
–
Precision VIN, VOUT, IIN, PIN, VAUX monitoring V 
(<±1%); I (<±1%); P (<±1.75%)
–
Power cycle with a single command
–
Blackbox fault recording of multiple events with 
relative time stamp stored in internal EEPROM
•
12-bit ADC with 250kHz sampling rate
•
Supports energy monitoring via Read_EIN 
command
•
External FET temperature sensing
2 Applications
•
Server and high performance computing
•
Network interface cards
•
Graphics and hardware accelerator cards
•
Datacenter switches and routers
•
Input hotswap and hotplug
•
PLC power management
•
24V to 48V industrial systems
3 Description
The LM5066Hx provides robust protection and 
precision monitoring for 12V, 24V and 48V systems 
with programmable UV, OV, ILIM, and fast short-
circuit 
protection 
for 
customized 
input 
power 
applications. Programmable power limit threshold 
along with adjustable fault timer (tFAULT) limits 
maximum power dissipation and ensures FET SOA 
protection under all conditions including startup and 
fault events. Two level overcurrent blanking with 
digital timers allows higher load transients to pass, 
enabling lower current limit settings and reducing 
requirements for strong SOA MOSFETs.
An integrated PMBus® interface enables remote 
monitoring, control, and configuration of the system 
in real time. Key parameters can be accessed 
remotely for telemetry, and various thresholds 
can be configured through PMBus or stored in 
internal EEPROM. The fast, accurate analog load 
current monitor supports predictive maintenance and 
dynamic power management including Intel PSYS 
and PROCHOT functionality to optimize server 
performance. A blackbox fault recording feature helps 
in debugging field failures.
The LM5066H2 features dual gate drive architecture 
which enables use of a single strong SOA FET 
to handle power stress during startup and fault 
conditions, combined with multiple small low RDS(ON) 
FETs for normal load current operation, reducing the 
total solution size. The devices are characterized for 
operation over a junction temperature range of –40°C 
to +125°C.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM5066H1PWPR
PWP (TSSOP 28)
9.70mm × 4.40mm
LM5066H2NLPR
NLP (QFN 35)
5.00mm x 7.00mm
(1)
For all available packages, see the orderable addendum at 
the end of the data sheet.
LM5066H
SNVSCT1A – OCTOBER 2025 – REVISED DECEMBER 2025
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, 
intellectual property matters and other important disclaimers. PRODUCTION DATA.

---PAGE_BREAK---
OUT
UVLO/EN
VIN
GATE
DIODE
R3
FB
OVLO
SDAI
SCL
PGD
SENSE
VDD
SMBus
Interface
SMBA
CL
RETRY
VAUX
VDD
VREF
TIMER
PWR
AGND
LM5066H1
VOUT
COUT
VIN
1
F
1
F
RPWR
ADR2
ADR1
ADR0
VDD
VIN_K
GND
SDAO
RSNS
R4
R1
CTIMER
R5
R6
CIN
D1
D2
QT
Q1
R2
IMON
RIMON
Cdvdt
LM5066H1 Simplified Schematic
OUT
UVLO/EN
VIN
GATE1
DIODE
R3
FB
OVLO
SDAI
SCL
PGD
SENSE
VDD
SMBus
Interface
SMBA
CL
RETRY
VAUX
VDD
VREF
TIMER
PWR
AGND
LM5066H2
VOUT
COUT
VIN
1
F
1
F
RPWR
ADR2
ADR1
ADR0
VDD
VIN_K
GND
SDAO
RSNS
R4
R1
CTIMER
R5
R6
CIN
D1
D2
Q1
R2
IMON
RIMON
Cdvdt
SYNC
SFT_STRT
QT
GATE2
Q2
Q3
Low RDS(ON) 
MOSFETs
Strong SOA 
MOSFET
LM5066H2 Simplified Schematic
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Device Comparison Table...............................................4
5 Pin Configuration and Functions...................................5
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................8
6.5 Electrical Characteristics.............................................8
6.6 Timing Requirements................................................17
6.7 PMBus Interface Timing Characteristics...................18
6.8 Typical Characteristics..............................................19
7 Detailed Description......................................................23
7.1 Overview...................................................................23
7.2 Functional Block Diagram.........................................24
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................30
7.5 Programming............................................................ 35
8 Application and Implementation..................................89
8.1 Application Information............................................. 89
8.2 Typical Application.................................................... 89
8.3 Power Supply Recommendations...........................100
8.4 Layout..................................................................... 100
9 Device and Documentation Support..........................103
9.1 Third-Party Products Disclaimer............................. 103
9.2 Receiving Notification of Documentation Updates..103
9.3 Support Resources................................................. 103
9.4 Trademarks.............................................................103
9.5 Electrostatic Discharge Caution..............................103
9.6 Glossary..................................................................103
10 Revision History........................................................ 103
11 Mechanical, Packaging, and Orderable 
Information.................................................................. 103
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4 Device Comparison Table
Table 4-1 summarizes the differences between the LM50666H1 and the LM5066H2.
Table 4-1. LM5066H1 vs LM5066H2
KEY FUNCTIONALITY
LM5066H1
LM5066H2
GATE2
✔
IMON
✔
✔
SYNC
✔
SFT_STRT
✔
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5 Pin Configuration and Functions
10
9
8
11
12
1
2
3
4
5
7
6
FB
RETRY
IMON
PWR
GATE
SENSE
VIN_K
NC
VIN
CL
PGD
OUT
UVLO/EN
TIMER
25
26
27
28
21
22
23
24
13
14
19
20
OVLO
AGND
SDAI
GND
SDAO
ADR2
ADR1
VDD
VAUX
ADR0
SMBA
SCL
18
17
16
15
VREF
DIODE
Figure 5-1. LM5066H1 PWP Package Top View 
SDAI
SDAO
SCL
SMBA
VREF
DIODE
VAUX
ADR2
ADR1
ADR0
VDD
FB
IMON
TIMER
PWR
PGD
SYNC
GND
SFT_STRT
GATE2
OUT
GATE1
SENSE
VIN_K
VIN
VIN
UVLO/EN
OVLO
AGND
GND
GND
CL
RETRY
GND
VIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
25
24
23
22
21
28
27
26
29
30
33
32
31
34
15
35
GND
Solder exposed pad to ground.
Figure 5-2. LM5066H2 QFN Package Top View 
Table 5-1. Pin Functions
PIN NAME
PIN NO.
DESCRIPTION
LM5066H1
LM5066H2
Exposed 
Pad
Pad
Pad
Exposed pad of package
Solder to the ground plane to reduce thermal resistance
OUT
1
13
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine 
the MOSFET VDS voltage for power limiting and to monitor the output voltage.
GATE1
2
14
Gate drive output
Connect to the external MOSFET's gate. Connect to single strong SOA MOSFET's 
gate for LM5066H2
SENSE
3
16
Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to 
this pin. If the voltage across RSNS reaches overcurrent threshold the load current 
is limited and the fault timer activates.
VIN_K
4
17
Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN
5
18, 19, 20
Positive supply input
This pin is the input supply connection for the device. A 10Ω resistor can be 
connected between VIN and input power supply. Connect a 100nF capacitor on 
this pin to ground for bypassing.
N/C
6
-
No connection
UVLO/EN
7
21
Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage 
turn ON threshold.
OVLO
8
22
Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn 
off threshold.
AGND
9
23
Circuit ground
Analog device ground. Connect to GND at the pin.
GND
10
9, 15, 24, 35
Circuit ground
SDAI
11
25
SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require 
unidirectional isolation devices.
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Table 5-1. Pin Functions (continued)
PIN NAME
PIN NO.
DESCRIPTION
LM5066H1
LM5066H2
SDAO
12
26
SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require 
unidirectional isolation devices.
SCL
13
27
SMBus clock
Clock pin for SMBus
SMBA
14
28
SMBus alert line
Alert pin for SMBus, active low
VREF
15
29
Internal reference
Internally generated precision reference used for analog to digital conversion. 
Connect a 1µF capacitor on this pin to ground for bypassing.
DIODE
16
30
External diode
Connect this to a diode configured MMBT3904 NPN transistor for temperature 
monitoring.
VAUX
17
31
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full scale input of 
2.97V.
ADR2
18
32
SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR1
19
33
SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR0
20
34
SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
VDD
21
1
Internal sub-regulator output
Internally sub-regulated 4.85V bias supply. Connect a 1µF capacitor on this pin to 
ground for bypassing.
CL
22
2
Current limit range
Connect this pin to GND or leave floating to set the nominal overcurrent threshold 
at 50mV. Connecting CL to VDD sets the overcurrent threshold to be 25mV.
FB
23
3
Power Good feedback
An external resistor divider from the output sets the output voltage at which the 
PGD pin switches.
SYNC
-
4
Synchronous turn ON and turn OFF of parallel controllers
Tie this pin of all parallel controllers for synchronous operation.
RETRY
24
5
Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to 
GND or left floating, the device will continually try to engage power during a fault. If 
the pin is connected to VDD, the device will latch off during a fault.
TIMER
25
6
Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout 
period, and restart timing.
PWR
26
7
Power limit set
An external resistor connected to this pin, in conjunction with the current sense 
resistor (RSNS), sets the maximum power dissipation allowed in the external series 
pass MOSFET.
IMON
27
8
Load current monitorAn external resistor needs to be connected from this pin to 
GND. IMON pin outputs current proportional to the load current.
PGD
28
10
Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above 
VFBTH and VGS1, VGS2 are high.
SFT_STRT
-
11
Soft start capacitor disconnectdvdt capacitor (Cdvdt) for inrush current limiting has 
to be connected from this pin to GND Internal switches connect Cdvdt to GATE1 
during startup/retry. After successful startup, the Cdvdt cap is connected to OUT
GATE2
-
12
GATE2 drive outputConnect to the external Low RDS(ON) MOSFETs gate.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input voltage
VIN, VIN_K, SENSE, UVLO/EN, PGD to GND
–0.3
100
V
Input voltage
VIN_K, SENSE to GND (10µs, 25℃ ≤ TJ ≤ 125℃, GATE1 = 
GATE2 = OFF)
–0.3
105
V
OVLO, FB, TIMER, PWR, SYNC, SCL, SDAI, SDAO, CL, 
ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY, IMON, 
SMBA, VREF to GND
–0.3
6
GATE1, GATE2, SFT_STRT to GND
–5
115
VIN_K to SENSE, AGND to GND
–0.3
0.3
GATE1, GATE2, SFT_STRT to OUT
–0.3
15
V
Output voltage
OUT to GND
-5
100
V
Operating junction temperature, TJ (2)
–40
150
°C
Storage temperature, Tstg
–65
150
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress 
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated 
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device 
reliability.
(2)
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V
Charged device model (CDM), per JEDEC specification JESD22- C101, 
all pins(2)
±500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
Input 
voltage
VIN, VIN_K, SENSE, OUT, UVLO/EN, PGD to GND
5.5
90
V
OVLO, CL, RETRY, ADR0, ADR1, ADR2, SYNC to GND
VVDD
Inuput 
Voltage
VAUX to GND
3
V
Output 
Voltage
OUT to GND
VVIN
V
Output 
Voltage
IMON to GND
3.3
V
Pull-up 
Voltage
SCL, SDAI, SDAO, SMBA
1.8
5
V
External 
Capacitanc
e
VDD, VREF to GND
1
µF
External 
Resistor
PWR to GND
120
kΩ
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
TJ
Operating Junction temperature(2)
–40
125
°C
(1)
Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test 
conditions, see Electrical Characteristics.
(2)
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
THERMAL METRIC(1)
LM5066H
UNIT
PWP
28 PINS
RθJA 
Junction-to-ambient thermal resistance
35.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.9
°C/W
RθJB
Junction-to-board thermal resistance
16.8
°C/W
ΨJT
Junction-to-top characterization parameter
0.5
°C/W
ΨJB
Junction-to-board characterization parameter
16.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application 
report.
6.5 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (VIN PIN)
VVIN
Operating input voltage range
5.5
90
V
I(VIN)
VIN pin current
VVIN = 48V, VUVLO/EN = 3V and VOVLO 
= 2V
4
7.8
mA
I(Q)
Total System Quiescent current, I(GND)
VVIN = 48V, VUVLO/EN = 3V and VOVLO 
= 2V
-4.3
-8
mA
VVIN = 12V, VUVLO/EN = 3V and VOVLO 
= 2V
-4.2
-8
mA
ISHDN
Total System Shutdown current, I(GND)
VVIN = 48V, VUVLO/EN = 0V
-4.4
-8
mA
PORR
Power-on reset rising threshold at VVIN 
to enable all functions and trigger 
insertion timer
VVIN increasing
4.6
4.8
V
PORF
Power-on reset falling threshold at 
VVIN to disable all functions
VVIN decreasing
4.2
4.26
V
VDD REGULATOR (VDD PIN)
VVDD
IVDD = 0mA
4.8
4.9
5
V
IVDD = 10mA, VVIN > 8V
4.8
4.9
5
V
IVDDILIM
VDD current limit
–20
–35
–42
mA
VVDD-PORR
VDD voltage reset threshold
VVDD rising
4.32
4.5
V
VVDD-PORF
VDD voltage reset threshold
VVDD falling
3.75
3.87
V
UVLO/EN, OVLO PINS
UVLOTH
UVLO threshold
VUVLO falling
2.38
2.48
2.60
V
UVLOHYS
UVLO hysteresis current
VUVLO = 1V
18
21
23
µA
UVLOBIAS
UVLO bias current
VUVLO = 3V
1
µA
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVLOTH
OVLO threshold
VOVLO rising
2.38
2.48
2.60
V
OVLOHYS
OVLO hysteresis current
VOVLO = 3V
–18
–21
–23
µA
OVLOBIAS
OVLO bias current
VOVLO = 1V
1
µA
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER LIMIT (PWR PIN)
VSNS,PLIM
Power limit sense voltage (VVIN_K – 
VSENSE)
VSENSE – VOUT = 48V, RPWR = 60kΩ
7.4
8.5
9.5
mV
VSENSE – VOUT = 48V, RPWR = 20kΩ
2.1
2.8
3.5
VSENSE – VOUT = 48V, RPWR = 20kΩ, 
0°C ≤ TJ ≤ 85°C
2.2
2.8
3.38
VSENSE – VOUT = 12V, RPWR = 60kΩ
30
34.2
38
VSENSE – VOUT = 12V, RPWR = 20kΩ
9.8
11.33
13.25
VSENSE – VOUT = 12V, RPWR = 20 kΩ, 
0°C ≤ TJ ≤ 85°C
10.15
11.33
12.43
IPWR
Source current from PWR pin
VPWR = 2.5V
-19.6
–20
-20.4
µA
RSAT(PWR)
Pull down of PWR pin when disabled
VUVLO = 0V
96
Ω
GATE CONTROL (GATE PIN)
IGATE1
Source current
Normal operation, VGATE1 – VOUT = 5V
 
-19.6
-21
-23.6
µA
Fault sink current
VUVLO = 2V
7.5
10
13.4
mA
POR circuit breaker sink current
VVIN_K – VSENSE = 60mV,
VGATE1 – VOUT = 5V,
CB/CL ratio bit = 0, CL = VDD
1.5
A
Regulation max sink current
 
VVINK – VSENSE = 30mV, CL = VDD
 
175
252
µA
IGATE2
Source current
Normal operation, VGATE2 – VOUT = 5V
-130
µA
Fault sink current
VUVLO = 2V
10
mA
POR circuit breaker sink current
VVIN_K – VSENSE = 60mV,
VGATE2 – VOUT = 5V,
CB/CL ratio bit = 0, CL = VDD
1.5
A
VGATE1Z
Reverse-bias voltage of GATE to OUT 
Zener diode, IZ = –100 µA
VGATE1 – VOUT,
VOUT = 0V
11
15.4
18.8
V
VGATECP
Peak charge pump voltage in normal 
operation (VV IN = VOUT)
VGATE1 – VOUT ,
VGATE2 – VOUT , VOUT = 48V
11
12.5
14
V
OUT PIN
IOUT-EN
OUT bias current, enabled
VV IN = VOUT, normal operation, VVIN = 
5.5V, 48V, 90V
-50
2
20
µA
IOUT-DIS
OUT bias current, disabled
VUVLO/EN = 0V, VVIN_K = VSENSE = 
VOUT, VVIN = 5.5V, 48V, 90V
40
55
µA
OUT bias current, disabled
VUVLO/EN = 0V, VOUT = -5V, VVIN_K = 
VSENSE
-290
-340
-400
OUT bias current, disabled
VUVLO/EN = 0V, VOUT = 0V, VVIN_K = 
VSENSE , VVIN = 5.5V, 48V, 90V
-30
-44
VOUT-DIS
OUT voltage, disabled
VUVLO/EN = 0V, VVIN_K = VSENSE
0.8
1.1
V
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
VCL
Current limit threshold voltage:
VVIN_K – VSENSE)
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 001
9.2
10
11.4
mV
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 010
12.5
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 100
15
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 100
15.65
17.5
19.4
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 101
20
DEVICE_SETUP1 [2] = 1;
DEVICE_SETUP2 [5:3] = 110
22.5
DEVICE_SETUP1 [2] = 0;
CL = VDD
23
25
27.2
DEVICE_SETUP1 [2] = 0;
CL = GND
46
50
54
VFBCL
Foldback Current Limit ratio:
VVIN_K – VSENSE)FBCL/VCL
VCL = 10mV;
DEVICE_SETUP3 [5:4] = 01
0.02
0.05
0.09
mV/mV
VCL = 10mV;
DEVICE_SETUP3 [5:4] = 10
0.07
0.1
0.14
VCL = 25mV;
DEVICE_SETUP3 [5:4] = 01
0.03
0.05
0.07
VCL = 25mV;
DEVICE_SETUP3 [5:4] = 10
0.08
0.1
0.12
VCBL1
Over Current Blanking1 threshold 
ratio:
(VVIN_K – VSENSE)CBL1/VCL
VCL = 10mV;
DEVICE_SETUP3 [1:0] = 00
1.14
1.25
1.4
mV/mV
VCL = 10mV;
DEVICE_SETUP3 [1:0]= 01
1.39
1.5
1.67
VCL = 10mV;
DEVICE_SETUP3 [1:0] = 10
1.64
1.75
1.93
VCL = 10mV;
DEVICE_SETUP3 [1:0] = 11
1.87
2
2.2
Over Current Blanking1 threshold 
ratio:
(VVIN_K – VSENSE)CBL1/VCL
VCL = 25mV;
DEVICE_SETUP3 [1:0] = 00
1.2
1.25
1.37
VCL = 25mV;
DEVICE_SETUP3 [1:0] = 01
1.43
1.5
1.63
VCL = 25mV;
DEVICE_SETUP3 [1:0] = 10
1.68
1.75
1.9
VCL = 25mV;
DEVICE_SETUP3 [1:0] = 11
1.9
2
2.15
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCBL2
Over Current Blanking2 threshold 
ratio:
(VVIN_K – VSENSE)CBL2/VCL
VCL = 10mV;
DEVICE_SETUP3 [3:2] = 00
1.38
1.5
1.66
mV/mV
VCL = 10mV;
DEVICE_SETUP3 [3:2] = 01
1.62
1.75
1.94
VCL = 10mV;
DEVICE_SETUP3 [3:2] = 10
1.85
2
2.22
VCL = 10mV;
DEVICE_SETUP3 [3:2] = 11
2
2.25
2.5
Over Current Blanking2 threshold 
ratio:
(VVIN_K – VSENSE)CBL2/VCL
VCL = 25mV;
DEVICE_SETUP3 [3:2] = 00
1.4
1.5
1.7
VCL = 25mV;
DEVICE_SETUP3 [3:2] = 01
1.65
1.75
1.92
VCL = 25mV;
DEVICE_SETUP3 [3:2] = 10
1.9
2
2.2
VCL = 25mV;
DEVICE_SETUP3 [3:2] = 11
2.1
2.25
2.5
ISENSE
SENSE pin current
Enabled,
VOUT = VVIN = VVIN_K = VSENSE = 48V
10
12.2
µA
Enabled,
VOUT = 0V, VVIN = VVIN_K = VSENSE = 
48V
26
30
VUVLO/EN = 0V, VOUT = 0V,
VVIN = VVIN_K = VSENSE = 48V
27
30
IVIN_K
VIN_K pin current
Enabled, VVIN_K = 48V, VCL = 25mV
VVIN_K – VSENSE = 25mV
285
330
µA
Enabled, VVIN_K = 48V, VCL = 25mV
VVIN_K – VSENSE = 5mV
265
320
µA
CIRCUIT BREAKER
VCB
Circuit breaker threshold voltage:
(VVIN_K – VSENSE)
VCL = 10 mV
DEVICE_SETUP2 [7:6] = 01
10
12
15.4
mV
VCL = 10 mV
DEVICE_SETUP1 [3] = 0
DEVICE_SETUP2 [7:6] = 00
17.5
20
24
VCL = 10 mV
DEVICE_SETUP2 [7:6] = 11
27.9
30
34.3
VCL = 10 mV
DEVICE_SETUP1 [3] = 1
DEVICE_SETUP2 [7:6] = 00
37.7
40
44.8
VCL = 25 mV
DEVICE_SETUP2 [7:6] = 01
27.65
30
33.97
VCL = 25 mV
DEVICE_SETUP1 [3] = 0
DEVICE_SETUP2 [7:6] = 00
47.18
50
55
VCL = 25 mV
DEVICE_SETUP2 [7:6] = 11
71
75
81.5
VCL = 25 mV
DEVICE_SETUP1 [3] = 1
DEVICE_SETUP2 [7:6] = 00
95.2
100
107.9
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RTCB
Circuit breaker to current limit ratio:
(VVIN_K – VSENSE)CB/VCL
VCL = 10 mV
DEVICE_SETUP2 [7:6] = 01
0.92
1.2
1.52
mV/mV
VCL = 10 mV
DEVICE_SETUP1 [3] = 0
DEVICE_SETUP2 [7:6] = 00
1.67
2
2.37
VCL = 10 mV
DEVICE_SETUP2 [7:6] = 11
2.57
3
3.45
VCL = 10 mV
DEVICE_SETUP1 [3] = 1
DEVICE_SETUP2 [7:6] = 00
3.47
4
4.53
Circuit breaker to current limit ratio:
(VVIN_K – VSENSE)CB/VCL
VCL = 25 mV
DEVICE_SETUP2 [7:6] = 01
1
1.2
1.39
VCL = 25 mV
DEVICE_SETUP1 [3] = 0
DEVICE_SETUP2 [7:6] = 00
1.79
2
2.25
VCL = 25 mV
DEVICE_SETUP2 [7:6] = 11
2.72
3
3.34
VCL = 25 mV
DEVICE_SETUP1 [3] = 1
DEVICE_SETUP2 [7:6] = 00
3.64
4
4.42
RTSCP
Short Circuit Protection threshold ratio:
(VVIN_K – VSENSE)SCP/VCB
1.5
mV/mV
FB PIN
FBTH
FB threshold falling
VUVLO = 3V and VOVLO = 0V
2.34
2.48
2.61
V
FBHYS
FB hysteresis current
-19
–21
-23
µA
FBLEAK
Off leakage current
VFB = 2.3V
1
µA
TIMER (TIMER PIN)
VTMRH
Upper threshold
3.74
3.9
4.1
V
VTMRL
Lower threshold
Restart cycles
 
1.05
1.2
1.3
V
End of eighth cycle re-enable 
threshold
 
0.3
ITIMER
 
Insertion time current
TIMER pin = 2V
–4.5
–5
–5.5
µA
Sink current, end of insertion time
TIMER pin = 2V
0.9
1.5
2.1
mA
Fault detection current, Constant 
Current Timer
 
TIMER pin = 2V
 
–69
–75
–83
µA
Fault sink current, Constant Current 
Timer
 
TIMER pin = 2V;
DEVICE_SETUP4 [6] = 0
2
2.5
3
µA
TIMER pin = 2V;
DEVICE_SETUP4 [6] = 1
70
75
83
Fault detection current, P2T Timer
 
TIMER pin = 0.5V,
(VSENSE – VOUT) x VSENSE = 20V x 
25mV;
DEVICE_SETUP4 [3:2] = 10 or 11
-62
µA
TIMER pin = 0.5V,
VDS x VSENSE = 48V x 5mV;
DEVICE_SETUP4 [3:2] = 10 or 11
-13.8
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P2t Threshold
P2t Timer threshold voltage
(VSENSE – VOUT) x VSENSE = 48V x 
5mV;
DEVICE_SETUP4 [3:2] = 10 or 11
0.9
1
1.1
V
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNC
ISYNC_LEAK
Leakage current on SYNC pin
VSYNC = VVDD, Normal Operation
800
nA
ISYNC
Sink current
VSYNC = 0.1V, Fault state,
OVLO high
20
mA
VSYNC
Steady State indication voltage
Steady state, PGD high
VVDD
V
Fault Indication voltage
Fault state, OVLO high
200
mV
POWER GOOD (PGD PIN)
PGDVOL
Output low voltage
ISINK = 2mA
120
200
mV
PGDIOH
Off leakage current
 
VPGD = 90V
2.5
µA
VPGD = VVDD
1
µA
VGS1_PGDH
VGATE1 – VOUT threshold for PGD high 
assertion
7.5
8.1
8.55
V
VGS1_G2L
VGATE1 – VOUT falling threshold for 
GATE2 Pull Down
7.85
V
VGS2_PGDH
VGATE2 – VOUT threshold for PGD high 
assertion
8.1
V
VDS_PGDH
VDS threshold for PGD high assertion
VSENSE – VOUT
1.3
1.9
2.5
V
VDS_G2L
VDS threshold for G2 Pull Down
VSENSE – VOUT
2.5
V
SFT_STRT
I(SFT_STRT, GATE1)
GATE1 to SFT_STRT charging current VOUT = VSFT_STRT = 0V
-22
µA
R(SFT_STRT, OUT)
Resistance of switch between 
SFT_STRT and OUT
VSFT_STRT = VOUT + 0.1V
2
Ω
IMON
GIMON
Transconductance Amplifier Gain 
(IIMON : VVIN_K - VSENSE)
VCL = 10mV , VVIN_K – VSENSE = 10mV
9.78
10
10.2
µA/mV
GIMON
Transconductance Amplifier Gain 
(IIMON : VVIN_K - VSENSE)
VCL = 25mV , VVIN_K – VSENSE = 25mV
9.8
10
10.2
µA/mV
ILKG(IMON)
IMON pin leakage
VIMON = 3.3V
-0.35
0.35
µA
FET_FAIL
VGS1_FFTH
GATE1 VGS threshold for FET_FAIL 
detection
3.3
4.1
4.7
V
VGS2_FFTH
GATE2 VGS threshold for FET_FAIL 
detection
4.1
V
VDS_FFTH
VDS threshold for FET_FAIL detection
2
V
VSNS_FFTH
VSNS threshold for FET_FAIL detection
1.9
2.5
3.2
mV
INTERNAL REFERENCE
VREF
Reference voltage
2.96
2.97
2.98
V
ADC AND AUX
Resolution
12
Bits
DNL
Differential non-linearity
ADC only
-0.67
1.5
LSB
INL
Integral non-linearity
ADC only
-2.1
2.4
LSB
Sampling rate
Samples per second
 
Any channel
250
kHz
tAQUIRE
Acquisition + conversion time
Any channel
4
µs
tRR
Acquisition round robin time
Cycle all channels
20
us
IAUX_LK
Leakage current on AUX
VAUX=3V, Normal Operation
500
nA
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TELEMETRY ACCURACY
IIN-ACC
Input current absolute accuracy
 
VCL = 10mV, VVIN_K – VSENSE = 10mV
-3
3
%
VCL = 10mV, VVIN_K – VSENSE = 10mV,
0℃ ≤ TJ ≤ 85℃
-2.5
2.5
VCL = 10mV, VVIN_K – VSENSE = 20mV,
ADC Full Scale = 2xVCL
-2
2
VCL = 10mV, VVIN_K – VSENSE = 20mV,
ADC Full Scale = 2xVCL, 0℃ ≤ TJ ≤ 
85℃
-1.5
1.5
VCL = 25mV, VVIN_K – VSENSE = 25mV
-1.22
1.22
VCL = 25mV, VVIN_K – VSENSE = 25mV,
0℃ ≤ TJ ≤ 85℃
-0.95
0.95
VCL = 25mV, VVIN_K – VSENSE = 5mV,
0℃ ≤ TJ ≤ 85℃
-4.7
4.7
VCL = 25mV, VVIN_K – VSENSE = 50mV,
ADC Full Scale = 2xVCL
-1.4
1.4
VCL = 25mV, VVIN_K – VSENSE = 50mV,
ADC Full Scale = 2xVCL, 0℃ ≤ TJ ≤ 
85℃
-1.2
1.2
VACC
VIN, VOUT absolute accuracy
VVIN, VVOUT = 48V
-1.18
1.18
%
VVIN, VVOUT = 48V, 0℃ ≤ TJ ≤ 85℃
-1
1
VVIN, VVOUT = 12 V
-1.64
1.64
VAUX absolute accuracy
VAUX = 2.8V
-0.47
0.47
VAUX = 2.8V, 0℃ ≤ TJ ≤ 85℃
-0.36
0.36
PIN-ACC
Input power accuracy, VCL = 10mV,
ADC Full Scale = 1xVCL
VVIN = 48V, VCL = 10mV,
VVIN_K – VSENSE = 10mV,
-3.62
3.62
%
VVIN = 48V, VCL = 10mV,
VVIN_K – VSENSE = 10mV, 0℃ ≤ TJ ≤ 
85℃
-3
3
Input power accuracy, VCL = 25mV,
ADC Full Scale = 1xVCL
VVIN = 48V, VCL = 25mV,
VVIN_K – VSENSE = 25mV,
-2
2
VVIN = 48V, VCL = 25mV,
VVIN_K – VSENSE = 25mV, 0℃ ≤ TJ ≤ 
85℃
-1.65
1.65
EIN Absolute error
Accumulated energy over 5 ms 
interval
VCL = 10mV, VVIN = 48 V,
VVIN_K – VSENSE = 10mV,
ADC Full Scale = 1xVCL, 0℃ ≤ TJ ≤ 
85℃
±3
%
VCL = 25mV, VVIN = 48 V,
VVIN_K – VSENSE = 25mV,
ADC Full Scale = 1xVCL, 0℃ ≤ TJ ≤ 
85℃
±2
REMOTE DIODE TEMPERATURE SENSOR
TACC
Temperature accuracy using local 
diode
25℃ ≤ TA ≤ 85℃
2
°C
Remote diode resolution
 
12
Bits
IDIODE
External diode current source
 
High level
-228
-250
-325
µA
Low level
-9
-10
-12.5
µA
Diode current ratio
23
25
27
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V ,VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PMBus PIN THRESHOLDS (SMBA, SDA, SCL)
VPULLUP_PMBus
PMBus interface pull ups
1.62
5
V
CPMB_BUS
PMBus Pin Capacitance - SCL
10
pF
PMBus Pin Capacitance - SDAI
10
PMBus Pin Capacitance - SDAO
10
VIL
SCL Input logic low
0.85
V
VIH
SCL Input logic high
1.25
V
VIL
SDAI Input logic low
0.85
V
VIH
SDAI Input logic high
1.25
V
VOL
Low-level output voltage - SDAO
IOL = 20mA from supply
0.4
V
ILEAK
Input leakage current for SCL
 
SCL = 5V
1
µA
Input leakage current for SDAI
 
SDAI = 5V
1
Input leakage current for SDAO
 
SDAO = 5V
1
Input leakage current for SMBA
SMBA = 5V
1
ADDRESS SELECT (ADR0, ADR1, ADR2)
VADRx
ADR0, ADR1 and ADR2 pin voltage
ADRx pin floating
1.63
V
CONFIGURATION PIN THRESHOLDS (CL, RETRY)
CLTH
Threshold voltage
2.6
V
RETRY TH
Threshold voltage
2.6
V
ILEAK
Input leakage current
CL, RETRY = 5 V
0.06
0.15
µA
6.6 Timing Requirements
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V, VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLODEL
UVLO delay
VUVLO/EN > UVLOTH to GATE high
20
28
35
µs
VUVLO/EN < UVLOTH to GATE low
4
7
10
µs
OVLODEL
OVLO delay
VO VLO < OVLOTH to GATE high
20
28
35
µs
VO VLO > OVLOTH to GATE low
4
7
10
µs
PGDDEL  
Power Good Assertion Delay, VGS2↑ to PGD↑VGS1 > 8V, VFB = 3V, VDS < 2V,
VGS2 > 8V to PGD high
5
µs
Power Good Assertion Delay, VFB↑ to PGD↑
VGS1 > 8V, VGS2 > 8V, VDS < 2V,
VFB > VFBTH to PGD high
0.75
3
VFB low to PGD de-assertion delay
VFB < VFBTH to PGD low
0.6
1
tGATE2DEL  
GATE2 turn ON delay
VDS< 2V to GATE2 high
22
µs
GATE2 turn OFF delay
VDS> 2V to GATE2 low
2.5
tCL
Current limit response time
tCBL1 and tCBL2 blanking timers expired,
VVIN – VSENSE stepped from 0 to 80 mV,
VCL = 50mV
12
30
µs
tCB
Circuit breaker response time
VVIN_K – VSENSE step from 0mV to 150mV to 
GATE low,
VCL = 50mV, DEVICE_SETUP2 [0] =0,
DEVICE_SETUP1 [3] = 0
0.27
0.8
µs
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6.6 Timing Requirements (continued)
Unless otherwise stated, the following conditions apply: VVIN=48V, –40°C < TJ < 125°C, VUVLO/EN=3V, VOVLO=0V, 
RPWR=20kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSCP
SCP response time
VVIN_K – VSENSE step from 0mV to 225mV to 
GATE low, VCL = 25mV, DEVICE_SETUP1 
[3] = 0
0.45
0.8
µs
tFAULT_DELAY
Fault to GATE low delay
 
VTIMER > VTMRH to GATE low
10
14
µs
tSYNC
VDD to 0V
CSYNC = 0nF,
VOVLO > OVLOTH to SYNC low
5.5
µs
tSYNC
0V to VDD
CSYNC = 0nF,
VOVLO < OVLOTH to SYNC high
5
µs
tBLTIMER1
Blanking Timer1 Range
0
95
ms
tBLTIMER2
Blanking Timer2 Range
0
95
ms
tWD
Watch Dog Timer Range
9.5
9500
ms
tRETRY
Digital Retry Delay Range
9.5
95000
ms
tINSDEL
Digital Insertion Delay Range
0.95
950
ms
6.7 PMBus Interface Timing Characteristics
over operating free-air temperature range (unless otherwise noted)
 
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PMBus Timing Characteristics
PMBCLKR
PMBus clock frequency range
PMBus Clock Requirements
0.05
1
MHz
tPMB-BUF
PMBus Free time between STOP and 
START conditions
0.5
µs
tPMB-HD-STA
Hold time after Repeated Start Condition
0.26
µs
tPMB-SU-STO
Stop condition Setup time
0.26
µs
tPMB-HD-DAT
SDA Hold Time
0
µs
tPMB-SU-DAT
SDA Setup Time
50
ns
tPMB-TIMEOUT
SCLK low timeout
25
35
ms
tPMB-LOW
SCLK low time
0.5
µs
tPMB-HIGH
SCLK high time
0.26
50
µs
tR-PMB
SDA/SCLK rise time
(VIL(MAX)-150 mV to VIH(MIN)+150 mV)
100 kHz Class
300
ns
400 kHz Class
300
ns
1000 kHz Class
120
ns
tF-PMB
SDA/SCLK fall time,
(VIH(MIN)+150 mV to VIL(MAX) + 150 mV)
100 kHz Class
1000
ns
400 kHz Class
300
ns
1000 kHz Class
120
ns
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6.8 Typical Characteristics
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
TJ - Junction Temperature (C)
I(VIN) - Input Current, Enabled (mA)
-50
-25
0
25
50
75
100
125
150
3
4
5
6
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-1. VIN Pin Current vs VVIN and TJ 
TJ - Junction Temperature (C)
IVIN_K - VIN_K pin Current (µA)
-50
-25
0
25
50
75
100
125
150
225
250
275
300
325
VVIN_K = 5.5V
VVIN_K = 12V
VVIN_K = 48V
VVIN_K = 60V
VVIN_K = 90V
Figure 6-2. VIN_K Pin Current vs VVIN and TJ 
TJ - Junction Temperature (C)
ISENSE - Sense pin Current (µA)
-50
-25
0
25
50
75
100
125
150
10.2
10.4
10.6
10.8
11
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-3. SENSE Pin Current vs VVIN and TJ 
TJ - Junction Temperature (C)
IOUT-EN - OUT pin Bias Current (µA)
-50
-25
0
25
50
75
100
125
150
-30
-20
-10
0
10
20
30
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-4. OUT Bias Current, Enabled vs VVIN and TJ 
TJ - Junction Temperature (C)
IOUT-DIS - OUT bias current, disabled (µA)
-50
-25
0
25
50
75
100
125
150
-35
-34
-33
-32
-31
-30
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-5. OUT Bias Current, Disabled vs VVIN and TJ 
TJ - Junction Temperature (C)
VVREF (V)
-50
-25
0
25
50
75
100
125
150
2.96
2.965
2.97
2.975
2.98
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-6. VREF Voltage vs VVIN and TJ 
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6.8 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
TJ - Junction Temperature (C)
UVLOTH - UVLO threshold (V)
-50
-25
0
25
50
75
100
125
150
2.48
2.485
2.49
2.495
2.5
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 80V
Figure 6-7. UVLO Threshold vs VVIN and TJ 
TJ - Junction Temperature (C)
UVLOHYS - UVLO Hysteresis Current (µA)
-50
-25
0
25
50
75
100
125
150
21
21.1
21.2
21.3
21.4
21.5
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 80V
Figure 6-8. UVLO Hysteresis Current vs VVIN and TJ 
TJ - Junction Temperature (C)
OVLOTH - OVLO threshold (V)
-50
-25
0
25
50
75
100
125
150
2.48
2.485
2.49
2.495
2.5
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 80V
Figure 6-9. OVLO Threshold vs VVIN and TJ 
Figure 6-10. OVLO Hysteresis Current vs VVIN and TJ 
Figure 6-11. GATE1 Voltage vs VVIN and TJ 
TJ - Junction Temperature (C)
IGATE1 - GATE1 Source Current (µA)
-50
-25
0
25
50
75
100
125
150
-22
-21.8
-21.6
-21.4
-21.2
-21
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-12. GATE1 Source Current vs VVIN and TJ 
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6.8 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
TJ - Junction Temperature (C)
IGATE1 - Fault Sink Current (mA)
-50
-25
0
25
50
75
100
125
150
8
10
12
14
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-13. GATE1 Sink Current vs VVIN and TJ 
Figure 6-14. Current Limit Threshold vs VVIN and TJ 
TJ - Junction Temperature (C)
VCL - Current Limit Threshold (mV)
-50
-25
0
25
50
75
100
125
150
17.5
17.6
17.7
17.8
17.9
18
VCL = 17.5mV
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-15. Current Limit Threshold vs VVIN and TJ 
TJ - Junction Temperature (C)
VCL - Current Limit Threshold (mV)
-50
-25
0
25
50
75
100
125
150
25
25.1
25.2
25.3
25.4
25.5
VCL = 25mV
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-16. Current Limit Threshold vs VVIN and TJ 
TJ - Junction Temperature (C)
VCL - Current Limit Threshold (mV)
-50
-25
0
25
50
75
100
125
150
50
50.1
50.2
50.3
50.4
50.5
VCL = 50mV
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-17. Current Limit Threshold vs VVIN and TJ 
Figure 6-18. Power Limit Threshold vs VVIN and TJ 
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6.8 Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
TJ - Junction Temperature (C)
VSNS,PLIM - Power Limit Sense Voltage (mV)
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
RPWR = 60k
VSENSE - VOUT = 12V
VSENSE - VOUT = 48V
Figure 6-19. Power Limit Threshold vs VVIN and TJ 
TJ - Junction Temperature (C)
GIMON - Transconductance Amplifier Gain (µA/mV)
-50
-25
0
25
50
75
100
125
150
9.8
9.9
10
10.1
10.2
VCL = 10mV
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 80V
VVIN = 90V
Figure 6-20. GIMON vs VVIN and TJ 
TJ - Junction Temperature (C)
GIMON - Transconductance Amplifier Gain (µA/mV)
-50
-25
0
25
50
75
100
125
150
9.8
9.9
10
10.1
10.2
VCL = 25mV
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 90V
Figure 6-21. GIMON vs VVIN and TJ 
TJ - Junction Temperature (C)
IIN-ACC - Input Current Telemetry Accuracy (%)
-50
-25
0
25
50
75
100
125
150
-0.5
-0.3
-0.1
0.1
0.3
0.5
VVIN = 5.5V
VVIN = 12V
VVIN = 48V
VVIN = 60V
VVIN = 80V
Figure 6-22. Input Current Telemetry Accuracy vs VVIN and TJ 
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7 Detailed Description
7.1 Overview
The LM5066Hx provides comprehensive hot swap control and power monitoring functionality for 12V, 24V and 
48V systems. Its inline protection circuitry limits inrush current when cards are inserted into live backplanes, 
preventing voltage sags and controlling dV/dt to connected loads. This minimizes disruption to other system 
components by avoiding unintended resets. The device also enables controlled shutdown when cards are 
removed.
In addition to a programmable current limit, the LM5066Hx monitors and limits the maximum power dissipation 
in the MOSFET to maintain operation within the device safe operating area (SOA). Extended current or power 
limiting conditions trigger shutdown of the MOSFETs device, with configurable retry options (none, 1, 2, 4, 8, 16, 
or infinite attempts). The circuit breaker function provides rapid shutdown of MOSFETs upon detection of severe 
overcurrent conditions. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits 
shut down the LM5066Hx when the system input voltage is outside the desired operating range.
Extensive configuration options are available through PMBus® interface or can be stored in internal EEPROM 
for autonomous operation without host intervention at power up. Comprehensive telemetry capabilities include 
monitoring of input voltage, output voltage, input current, input power, temperature, and an auxiliary input. 
The device features input voltage, current, power and temperature peak and programmable averaging of key 
parameters. Programmable warning thresholds for monitored parameters can trigger the SMBA pin through the 
PMBus interface. Advanced telemetry features include high speed ADC sample buffering ("digital oscilloscope") 
and Blackbox fault recording to simplify debugging and enable predictive maintenance.
The integrated high accuracy, high bandwidth analog load current monitor enables precise load current 
measurement in both steady state and transient conditions, facilitating advanced dynamic platform power 
management techniques such as Intel PSYS to optimize system power usage and throughput without 
compromising safety.
The LM5066H2 features dual gate driver architecture that optimizes board space and reduces component 
costs in high power applications requiring multiple hot swap FETs. The primary gate driver (GATE1) controls a 
single robust SOA FET specifically designed to handle demanding conditions such as startup, current limiting, 
and power limiting during fault events. The secondary gate driver (GATE2) becomes active only after the 
main FET reaches full enhancement, allowing system designers to select secondary FETs based solely on 
low RDS(ON) characteristics without requiring extensive SOA capability. This architecture significantly reduces 
component count and board space while maintaining robust system protection. The device's 100μA sourcing 
current capability ensures rapid recovery during transient conditions, preventing system resets during events 
such as adjacent card removal.
The LM5066H2 incorporates advanced soft start capacitor disconnect functionality that provides controlled 
startup sequencing while automatically disconnecting the soft start capacitor during normal operation. This 
feature enables the use of smaller hot swap FETs without sacrificing transient response performance, further 
optimizing system design. The device includes comprehensive diagnostic capabilities to detect damage to 
external MOSFETs connected to both GATE1 and GATE2 pins, enhancing system reliability and facilitating 
troubleshooting.
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7.2 Functional Block Diagram
PWR
GATE1
20 
A
20
A
Insertion
Timer
Fault  
Timer
Fault  
Discharge
1.2 V
TIMER
Current Limit & 
Blanking Threshold
CHARGE
PUMP
20 
A
TIMER AND GATE  
LOGIC CONTROL
Power Limit  
Threshold
10mA    
GATE
CONTROL
OUT
1.5 mA  
End  
Insertion  
Time
0.3 V
LM5066Hx
Power Limit  
Control
4.75 V
VIN
Enable 
POR
VCL / VCBLx
1.5A
1/30
S/H
1/30
VAUX
AMUX
EEPROM
SMBUS
INTERFACE
DIODE
ADR0
ADR1
ADR2
SCL
SDAO
SMBA
ADDRESS  
DECODER
TELEMETRY
STATE  
MACHINE
CL
RETRY
Diode  
Temp  
Sense
VDD
REG
VDD
2.48 V
2.46 V
2.48 V
AGND
UVLO/EN
OVLO
12 bit
ADC
ov
uv
VDS<2V
Snapshot
VDS
IDS
Current 
Limit 
Sense
VCB / VSCP
Circuit Breaker
Threshold
SDAI
2.97 
VRef
VREF
4.8 
A
75 
A
Current Limit/
PGD
FB
OUT
SENSE
VIN K
_
VIN
20
A
21
A
3.9V
GND
VGS1>8V
130
A
10mA    
1.5A
GATE2*
OUT
∝IDS
GATE1
OUT
SFT_STRT*
IMON
OUT
OUT
SYNC*
VGS2>8V
* Pin available in LM5066H2 only
1 V
∝P2
Inrush
10
A/mV
WORKING REGISTERS
FET FAIL 
DETECTION
Digital Timers
S
R
Q
VSNS
VDS
VGS1
VGS2
7.3 Feature Description
7.3.1 Current Limit
The LM5066Hx provides current limit protection with eight programmable thresholds ranging from 10mV to 
50mV. Current limiting activates when the voltage across the sense resistor RSNS (between VIN_K and SENSE 
pins) exceeds the selected threshold. Two thresholds can be set directly using the CL pin, 25mV when CL 
is connected to VDD and 50mV when CL is connected to GND. All eight (8) thresholds are available by 
programming the DEVICE_SETUP1 and DEVICE_SETUP2 registers through the PMBus interface.
During an overcurrent event, the device offers two protection modes: overcurrent blanking and current limiting. 
These modes can operate independently or sequentially based on configuration.
In overcurrent blanking mode, the device allows the load current to flow without limiting it for a set time period, 
as long as it remains below the circuit breaker threshold (VCB). The LM5066Hx features two overcurrent blanking 
thresholds with separate timers:
•
VCBL1 with timer tCBL1 for moderate overcurrents
•
VCBL2 with timer tCBL2 for higher overcurrents
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These thresholds and timers are configured in the DEVICE_SETUP3 and OC_BLANKING_TIMERS registers. 
Typically, VCBL1 is set higher than VCL, and VCBL2 is set higher than VCBL1. For load currents between VCL and 
VCBL2, the tCBL1 timer activates. For load currents between VCBL1 and VCBL2, the tCBL2 timer activates.
The timer resets if the current drops below the respective threshold before it expires. If either timer expires 
due to prolonged overload, the device transitions to current limiting mode. In the LM5066H2, GATE2 turns off 
immediately when either timer expires. Overcurrent blanking mode can be disabled by setting tCBL1 and tCBL2 to 
0μs.
In current limiting mode, the GATE voltage is regulated such that the current through MOSFET driven by GATE1 
is limited to the set current limit threshold. The fault timer activates during current limiting. If the load current 
falls below the current limit threshold before the fault timer expires, normal operation resumes. If the current limit 
persists beyond the fault timeout period set by CTMR, GATE1 turns off. Current limiting can be disabled by setting 
bit 7 in DEVICE_SETUP3. When disabled, both GATE1 and GATE2 turn off after the blanking phase when either 
of the blanking timer expires. When a current limit fault occurs, the device sets fault flags in the STATUS_INPUT 
(7Ch), STATUS_WORD (79h), and DIAGNOSTIC_WORD (E1h) registers, and asserts the SMBA pin. SMBA 
signaling can be disabled using the ALERT_MASK (D8h) register. For reliable operation, the RSNS resistor value 
should not exceed 200mΩ to avoid instability in the current limit control loop.
Over Current Limit Threshold,  
Over Current Blanking2 Threshold,  
Circuit Breaker Threshold,  
No Blanking operation*
There is No Blanking* or Regulation operation  
For VSNS > VCB > VSCP , GATE1 and GATE2 turned OFF immediately
There is No Load Current Blanking or Limiting in any condition
For
CBL1
t
*Load current is blanked for 100µs if
VIN is rising and VOUT is not discharging    
Controller will enter Current limit mode,  
Load Current will be Regulated to VCL  for  
Regulation fault timer duration  
Reduced Current Limiting threshold (Only during Startup and Retry)
Short Circuit Protection Threshold,  
VSCP
VCB
VCBL2
Over Current Blanking1 Threshold,  
VCBL1
VCL
Foldback Current Limit Threshold,  
VFBCL
Digital Blanking Timer, t
Load current is blanked for a maximum of  CBL1  duration
CL  < VSNS < VCBL2,  
For V
For VCBL1  < VSNS< VCBL2,  
duration
tCBL2  
Load Current is blanked for a maximum of  
Digital Blanking Timer, t CBL2
For  VCBL2 < VSNS < VCB , Controller will enter Current Limit mode immediately
VSNS > VSCP,  GATE1 and GATE2 turned OFF immediately
,
After Expiry of  tCBL2 or  tCBL2
Figure 7-1. Current Limit, Blanking and Circuit Breaker Thresholds
Table 7-1. Current Limit, Foldback Current Limit, Overcurrent Blanking, Circuit Breaker and Other 
Threshold Settings
Parameter
No. of Configurable Thresholds
Thresholds Values
Analog / Digital
Overcurrent Limit Threshold, VCL
8
10mV, 12.5mV, 15mV,17.5mV, 
20mV, 22.5mV and 25mV, 50mV
Analog
Overcurrent Blanking1 Threshold, 
VCBL1
4
1.25xVCL, 1.5xVCL, 1.75xVC, 
2xVCL
Analog
Overcurrent Blanking2 Threshold, 
VCBL2
4
1.5xVCL, 1.75xVCL, 2xVCL, 
2.25xVCL
Analog
Circuit Breaker Threshold, VCB
4
1.2xVCL, 2xVCL, 3xVCL,4xVCL
Analog
Short-circuit Protection 
Threshold, VSCP
1
1.5xVCB
Analog
Foldback Factor during StartUp
3
0.05xVCL, 0.1xVCL
Analog
Overcurrent Blanking Timer1
16
0ms - 95ms
Digital
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Table 7-1. Current Limit, Foldback Current Limit, Overcurrent Blanking, Circuit Breaker and Other 
Threshold Settings (continued)
Parameter
No. of Configurable Thresholds
Thresholds Values
Analog / Digital
Overcurrent Blanking Timer2
16
0ms -9.5ms, 95ms
Digital
Circuit Breaker Blanking Time
1
100us
Analog
Regulation Timer
(Constant Current Timer / P2t 
Timer)
Set with TIMER pin
Configurable using CTIMER
Maximum Value: 0ms – 95ms
Analog
P2t Timer - Insertion Timer
4
0.95ms – 950ms
Digital
P2t Timer - Retry Timer
16
9.5ms – 95s
Digital
Watch Dog Timer during Startup/
Retry
16
9.5ms – 9.5s
Digital
7.3.2 Foldback Current Limit
The LM5066Hx features current foldback capability during startup, limiting current to either 5% or 10% of the 
normal current limit threshold. This feature enables safe startup into capacitive loads without requiring external 
dV/dt capacitors on the GATE1 or SFT_STRT pins. The foldback factor can be selected using bits 4:5 in the 
DEVICE_SETUP3 register, and the feature can be disabled through the same register if not needed.
A Watchdog Timer function monitors if the hot swap startsup within the expected timeframe. The timer duration 
is programmable from 10 ms to 10 s through the WD_CONFIG register and should be set longer than the 
anticipated startup time. The MOSFET connected to GATE1 must be selected to handle the foldback current for 
the entire watchdog timer duration to ensure reliable operation during startup conditions.
7.3.3 Soft Start Disconnect (SFT_STRT)
The LM5066H2 features an advanced soft start mechanism that controls inrush current into output capacitors 
using a capacitor connected between the SFT_STRT pin and GND. This configuration allows precise control of 
startup current based on the below equation.
Unlike conventional hot swap controllers that connect the dV/dt capacitor directly to the gate, the LM5066H2 
implements a switching architecture between the GATE1 and SFT_STRT pins. This design includes a 
disconnect switch between GATE1 and SFT_STRT, plus a discharge switch between SFT_STRT and OUT. 
During initial hot plug and insertion delay, the GATE1 to SFT_STRT switch remains open while the SFT_STRT to 
OUT switch is closed. During startup, the SFT_STRT pin connects to GATE1 to control slew rate. Once normal 
operation begins, the SFT_STRT pin disconnects from GATE1 and connects to OUT.
This architecture solves multiple issues that exist in traditional designs: it prevents slow response during current 
or power limiting in steady state, avoids delayed GATE turn off during circuit breaker or short-circuit protection 
events, and eliminates slowed turn on during immediate retry after false circuit breaker faults that could further 
depress output voltage.
7.3.4 Circuit Breaker
The LM5066Hx provides programmable circuit breaker (CB) protection with multiple threshold options. The 
circuit breaker threshold can be configured at 1.2x, 2x, 3x, or 4x of the current limit threshold by programming 
the DEVICE_SETUP1 and DEVICE_SETUP2 registers. This feature protects against rapid current increases, 
such as short-circuits, where the current through the sense resistor (RSNS) may exceed the circuit breaker 
threshold before the current limit loop responds.
When the circuit breaker threshold is exceeded, both GATE1 and GATE2 are rapidly turned off using a strong 
1.5A pulldown current. If required, the device can be configured using bit 7 of DEVICE_SETUP4 register to 
retry immediately after a 30μs deglitch time by releasing the pulldown current and enabling GATE1. During 
this immediate retry, the gate voltage is controlled by the dV/dt, current limit, or power limit functions as 
needed. If overcurrent or power limiting persists, the regulation timer activates. Should the timer reach 3.9 V 
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before the limiting condition resolves, GATE1 is turned off using either 10mA or 1.5A pulldown current. During 
immediate retry, GATE1 turn on can be slowed by the limited 21μA source current and any external dV/dt 
capacitor connected to the GATE1 or the SFT_STRT pin. To improve output voltage recovery speed after false 
circuit breaker trips, the device includes a fast recovery feature that can disable the dV/dt capacitor connection 
and/or enable GATE2 alongside GATE1. This fast recovery logic can be enabled or disabled using bit 1 in the 
DEVICE_SETUP2 register.
For systems with multiple hot pluggable cards on a common backplane (like blade servers and telecom 
equipment), supply transients can cause current spikes large enough to falsely trigger the circuit breaker. To 
prevent nuisance tripping, the LM5066Hx implements a protection algorithm that blanks the circuit breaker 
threshold for 100 μs, allowing transients to settle without shutting down the system. During this blanking period, 
a fixed short-circuit protection (SCP) threshold (1.5x the circuit breaker threshold) remains active to protect 
against severe overcurrent events. If this SCP threshold is exceeded, the device turns off both gates with 1.5A 
pulldown. This supply transient blanking feature can be enabled or disabled using bit 0 in the DEVICE_SETUP2 
register.
Circuit breaker events set fault flags in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and 
DIAGNOSTIC_WORD (E1h) registers, and assert the SMBA pin unless disabled via the ALERT_MASK (D8h) 
register. Circuit breaker configuration can be modified through the DEVICE_SETUP (D9h) register.
7.3.5 Power Limit
The LM5066Hx features MOSFET power limiting to protect the external FET from operating outside its safe 
operating area (SOA). This function monitors power dissipation in the MOSFET driven by GATE1 by measuring 
both its drain-source voltage (SENSE to OUT) and drain current through the sense resistor RSNS (VIN_K to 
SENSE). The power limit threshold is set using a resistor at the PWR pin.
When power dissipation reaches the limiting threshold, the device turns off GATE2 and modulates GATE1 
voltage to regulate current through Q1. During power limiting, the fault regulation timer activates. If the power 
limit condition persists beyond the Fault Timeout Period set by the CTMR capacitor, GATE1 turns off. This event 
sets the IIN_OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) 
register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin is 
also asserted unless disabled through the ALERT_MASK (D8h) register.
For applications where input voltage can experience step changes (such as 45V to 55V), the device includes a 
power limit blanking mode. During normal operation, as VDS increases, the current limit threshold decreases in 
a constant power limit profile. This can cause the device to remain in power limit mode for the entire fault timer 
duration under high loads, potentially shutting down the FETs. Power limit blanking addresses this by disabling 
constant power limit based current foldback when VDS is below the VPLIM,BL threshold. This allows more current 
to flow and charge the output capacitor while serving the load, helping the output voltage reach the input voltage 
without MOSFET shutdown. The VPLIM,BL threshold is configurable through bits 0:1 of the DEVICE_SETUP4 
register.
In the VDS region below VPLIM,BL, FET power dissipation will exceed PLIM since current limit foldback is disabled 
in power limit blanking mode. This feature operates only in steady state (when, PG=High) and is not available 
during startup or retry conditions. To maintain FET operation within its SOA, a digital timer activates during 
power limit blanking mode. This timer should be configured by the designer and is typically set shorter than the 
regulation timer duration.
The device provides flexible configuration options for different operating conditions, allowing selective enabling 
of SFT_STRT to GATE1 connection, current limiting, power limit blanking mode, overcurrent blanking, and 
foldback current limiting based on system requirements.
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VDS
ILIMIT
VDS,MAX
ILIM,CL
ILIM,PL_MIN
VPLIM_BL
Constant Power Limit Profile
Power Limit Blanking Profile
Figure 7-2. Power Limit Profiles
7.3.6 UVLO
The LM5066Hx enables MOSFETs only when the input supply voltage is within the operating range defined 
by programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. The UVLO threshold at 
VIN is typically set using a resistor divider network. When VIN is below the UVLO threshold, an internal 20 μA 
current source at the UVLO pin activates while the current source at OVLO remains off. During this condition, the 
MOSFETs are held off by a strong pulldown current (10 mA or 1.5A) between the GATEx and OUT pins. As VIN 
increases and raises the UVLO pin voltage above its threshold, the 21μA current source at UVLO switches off. 
This action increases the voltage at the UVLO pin, providing hysteresis for stable threshold operation.
Once the UVLO/EN pin exceeds its threshold and the insertion time delay expires, GATE1 turns on with a 20 μA 
current source. GATE2 activation follows after GATE1's VGS reaches more than 8V and the voltage across the 
FET (VDS) drops below 2V.
The Application and Implementation section provides detailed procedures for calculating threshold setting 
resistor values. For minimum UVLO level configuration, the UVLO/EN pin can connect directly to VIN, allowing 
MOSFET activation after insertion time when VIN reaches the power on reset (POR) threshold. After power 
up, an UVLO condition sets multiple status flags, the INPUT bit in the STATUS_WORD (79h) register, the 
VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the 
DIAGNOSTIC_WORD (E1h) register. The SMBA pin pulls low during this condition unless disabled through the 
ALERT_MASK (D8h) register.
7.3.7 OVLO
When VIN causes the OVLO pin voltage to exceed its threshold, the MOSFETs are turned off through a strong 
pulldown current (10mA or 1.5A) at the GATE pin, disconnecting load from the power supply. During an OVLO 
condition, an internal 21 μA current source activates at the OVLO pin, increasing the voltage to create threshold 
hysteresis for stable operation.
When VIN drops below the OVLO threshold, GATE1 reactivates first, followed by GATE2 turn on, but only 
after GATE1's gate-source voltage exceeds 8V and the drain-source voltage falls below 2V. An OVLO event 
sets multiple status flags: the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the 
STATUS_WORD (79h) register, and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) 
register. The SMBA pin pulls low during this condition unless disabled through the ALERT_MASK (D8h) register.
The Application and Implementation section provides procedures for calculating the appropriate threshold setting 
resistor values.
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7.3.8 Power Good
The LM5066Hx features a Power Good indicator pin (PGD) which requires an external pullup resistor to provide 
status indication to downstream circuits. The PGD pin's off-state voltage can operate above or below the VIN 
and OUT voltages.
The PGD signal asserts HIGH when all of the below conditions are met,
•
FB pin voltage exceeds the PGD threshold
•
Both GATE1-OUT and GATE2-OUT voltages indicate full enhancement (VGS1 >8V and VGS2 >8V)
•
Voltage across the FET (VDS) is less than 2V
The PGD signal pulls LOW when,
•
FB pin voltage drops below the PGD falling threshold
The output voltage threshold is typically set using a resistor divider network from output to the feedback pin. 
However, other voltages can be monitored as long as the FB pin voltage remains within its maximum rating. 
For threshold hysteresis, the device includes a 21μA current source at the FB pin. This current source remains 
disabled when FB voltage is below threshold. As output voltage increases and FB exceeds threshold, the current 
source activates, sourcing current from the pin to raise FB voltage. The PGD pin status can be read through the 
PMBus interface via either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
7.3.9 VDD Sub-Regulator
The LM5066Hx includes an internal linear sub-regulator that converts the input voltage to a 4.9V supply rail for 
powering low voltage circuits. This VDD output can serve as the pullup supply for the CL, RETRY, ADR2, ADR1, 
and ADR0 pins if they are to be tied high. It can also function as the pullup supply for the PGD pin and SMBus 
signals (SDA, SCL, and SMBA).
The VDD sub-regulator is designed for light load applications and should not power other integrated circuits. 
For device protection, the VDD pin includes current limiting set at 30 mA to prevent damage during short-circuit 
conditions. Proper operation requires a ceramic bypass capacitor of at least 1 μF connected as close as possible 
to the VDD pin.
7.3.10 Remote Temperature Sensing
The LM5066Hx features remote temperature sensing using an external MMBT3904 NPN transistor. Connect 
the transistor's base and collector to the DIODE pin and the emitter to the LM5066Hx ground. Position the 
transistor near the component requiring temperature monitoring, such as the hot swap pass MOSFET (Q1). The 
temperature measurement works by detecting changes in diode voltage in response to current steps from the 
DIODE pin. This pin supplies a constant 10μA with periodic 250μA pulses every 50μs to measure temperature. 
For accurate readings, minimize parasitic resistance between the DIODE pin and transistor, implement a Kelvin 
connection from the transistor emitter to device ground, and place a 1 nF bypass capacitor in parallel with the 
transistor to reduce noise.
Temperature readings are accessible through the READ_TEMPERATURE_1 PMBus command (8Dh). The 
default temperature fault and warning thresholds can be configured through the PMBus interface using 
OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. When not using the temperature sensing 
function, ground the DIODE pin. Note that inaccurate temperature readings may occur when input voltage falls 
below the minimum operating level (5.5V), as this causes VREF to drop below its nominal 2.97 V. At higher 
ambient temperatures, this condition may produce readings exceeding the OT_FAULT_LIMIT, triggering a fault 
that disables Q1. To recover, clear faults and reset the device by writing 0h followed by 80h to the OPERATION 
(03h) register.
7.3.11 Damaged MOSFET Detection
The LM5066Hx includes MOSFET fault detection capability to identify damaged external MOSFETs under 
specific conditions. The device monitors for two main fault types:
Drain-to-source or drain-to-gate faults are detected when,
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•
During insertion, the voltage across the sense resistor exceeds 2mV (VSNS > 2mV) or the voltage across the 
FET falls below 2V (VDS < 2V)
•
After startup, if GATE turns off due to any fault and the sense resistor voltage remains above 2 mV after 1ms
Gate-to-source or drain-to-gate faults are detected when,
•
VGS1 remains below 4V for more than 500ms after GATE1 is set high
•
VGS2 remains below 4V for more than 500ms after GATE2 is set high
When a drain fault is detected, multiple status registers are updated, the FET FAIL bit in STATUS_WORD 
(79h), the EXT_MOSFET_SHORTED bit in STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h), 
and the FET_FAULT_DRAIN bit in STATUS_MFR_SPECIFIC. The SMBA pin asserts unless disabled via the 
ALERT_MASK register (D8h). The device remains in latched-off state until OPERATION OFF command followed 
by OPERATION ON is issued or UVLO/EN toggle or POWER_CYCLE command is issued or supply power cycle 
event occurs.
For gate faults, the device sets the FET FAIL bit in STATUS_WORD (79h), the EXT_MOSFET_SHORTED 
bit in STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h). Additionally, for GATE1 faults, the 
FET_FAULT_GATE1 bit in STATUS_MFR_SPECIFIC is set, while for GATE2 faults, the FET_FAULT_GATE2 bit 
is set. After detecting GATE type fault, GATE1 and GATE2 can be configured to turn off by setting bit 6 in the 
GATE_MASK (D7h) register. If configured to turn off after GATE type fault, the device retries as per configuration 
setting.
7.3.12 Analog Current Monitor (IMON)
The LM5066Hx features a precision analog current monitor that outputs a current proportional to the load current 
through the external MOSFET. This current mode output appears at the IMON pin with a gain of 10μA/mV 
relative to the voltage across the sense resistor (RSNS).
The current output design allows the signal to be routed across long board distances without introducing errors 
from voltage drops or noise coupling from adjacent traces. In parallel hot swap configurations, multiple IMON 
pins can be tied together to provide a summed current measurement representing total system current.
For measurement purposes, the IMON current can be converted to a voltage by connecting a resistor (RIMON) 
from the IMON pin to ground. The resulting voltage (VIMON) provides an accurate representation of load current 
according to the equation below.
The IMON circuit delivers high bandwidth and accuracy across varying load and temperature conditions, 
independent of board layout and system operating parameters. This performance makes it ideal for advanced 
dynamic platform power management implementations like Intel PSYS or PROCHOT, enabling systems to 
maximize power usage and throughput without compromising safety or reliability. If the IMON feature is not 
required in the application, the pin can be left floating without affecting device operation.
7.4 Device Functional Modes
7.4.1 Power Up Sequence
The LM5066Hx operates across a 5.5V to 80V input range with 100V transient capability. During initial power 
up, the device prevents accidental MOSFET turn on by applying a 10mA pulldown current between the GATEx 
and OUT pins, protecting against Miller capacitance charging effects. The TIMER pin starts at ground potential. 
When VIN reaches the power on reset (POR) threshold, the insertion delay sequence begins. During this period, 
a 5μA current source charges the external timing capacitor (CTMR) while the 10mA pulldown maintains the 
MOSFET in the off state. This delay allows input voltage transients to settle before enabling the pass device. 
The insertion delay ends when the TIMER pin reaches 3.9V, at which point CTMR rapidly discharges through an 
internal 1.5mA current sink.
If VIN exceeds the UVLO threshold after the insertion delay, the GATE1 pin activates with a 21μA current source 
to charge the MOSFET gate. An internal 16.5V Zener diode limits the maximum gate-source voltage. For the 
LM5066H2, GATE2 turns on with a 130 μA source current once GATE1 VGS exceeds 8V and the VDS falls below 
2V. As output voltage rises, the device monitors current flowing through the MOSFETs and power dissipation. 
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During inrush current or power limiting, a 75μA fault timer current charges CTMR. If limiting conditions resolve 
before TIMER reaches 3.9V, the current source turns off and CTMR discharges through a 2.5μA current sink. If 
TIMER reaches 3.9V while still in limiting conditions, a fault is asserted and GATE1 turns off.
The CONFIG_PRESET bit in the STATUS_MFR_SPECIFIC register (80h) remains set until cleared with a 
CLEAR_FAULTS command. A configurable watchdog timer (10ms to 10s) monitors power up progress. This 
timer starts when GATE1 is enabled, and if PGD doesn't assert within the set duration, the WD timer fault is 
indicated in the STATUS_MFR_SPECIFIC_2 register. This fault can be configured to turn off both GATE1 and 
GATE2 through the GATE_MASK register.
The device SMBus address is determined by ADR0, ADR1, and ADR2 pin states at power up, latched after VDD 
exceeds its 4.3V POR threshold. Address capture can be postponed by holding the VREF pin low, which also 
resets logic and clears operating memory. Upon release, the address latches when VREF exceeds 2.55V. For 
custom addressing, the hardware set address can be overridden by programming the PMBUS_ADDR register 
while leaving the address pins floating.
Normal Operation
Insertion Time
POR
Load
Current
Inrush
Limiting
FB
4.8 
A
75 
A
3.9 V
2.5 
A
21 
A source
GATE
TIMER
UVLO
VIN
VIN
10mA pull-down
Safety 
Pull-Down
ILIMIT
2.46 V
t2
t1
t3
PGD
Figure 7-3. Power Up Sequence (Current Limit Only)
7.4.2 Gate Control
The LM5066H1 offers single gate drive capable of driving multiple MOSFETs in parallel. LM5066H2 features 
dual gate drive architecture that optimizes MOSFET selection for high power hot swap applications. GATE1 
drives a single robust SOA MOSFET in dual gate configuration or multiple MOSFETs in single gate mode. With 
a 21μA gate source current, GATE1 provides controlled turn on for effective inrush current limiting or power limit 
based startup. A dV/dt capacitor can connect directly from GATE1 to GND for LM5066H1 or across SFT_STRT 
to GND for LM5066H2 to further manage inrush current. During current limiting or power limiting conditions, the 
device regulates GATE1 while keeping GATE2 off.
In dual gate operation, GATE2 drives multiple low RDS(ON) MOSFETs for normal operation. To protect these 
MOSFETs, GATE2 turns off whenever VDS exceeds 2V, preventing power stress during startup, short-circuit 
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conditions, or current/power limiting events. GATE2 activates only after GATE1 VGS exceeds 8V and VDS drops 
below 2V. The higher gate source current (130μA) enables rapid turn on of multiple parallel MOSFETs.
GATE1 and GATE2 are turned OFF for LM5066Hx if any of the below events occur,
•
Current exceeds the current limit threshold after Overcurrent blanking and regulation fault timer expires
•
Power dissipation in the MOSFET exceeds the power limit threshold and regulation fault timer expires
•
Undervoltage or overvoltage conditions
•
Circuit breaker or short-circuit protection
•
Over temperature or damaged MOSFET detection or watchdog expiry faults
•
PMBus Commands, OPERATION or POWER CYCLE command sets output disable
In steady state when any of the below conditions occur, GATE2 is turned OFF and GATE 1 remains ON or in 
regulation,
•
VDS exceeds 2V for any reason
•
Start of Current limiting or power limiting operation
An internal charge pump supplies gate voltage to both outputs, producing approximately 13.5V at the gates 
under normal operation. During initial power up, a 10 mA pulldown prevents unwanted MOSFET activation from 
Miller capacitance effects.
During insertion time, both gates are held low by 10 mA pulldown currents. After insertion, GATE1 voltage 
modulates to maintain current and power within programmed limits while the TIMER capacitor charges. If limiting 
conditions resolve before TIMER reaches 3.9 V, the capacitor discharges and normal operation begins. If limiting 
persists until TIMER reaches 3.9 V, GATE1 pulls low until a retry occurs.
The LM5066Hx offers configurable gate pulldown strength (10 mA or 1.5 A) for various fault conditions, providing 
flexibility to match system requirements.
Parameter
Condition
GATE1
GATE2
Source Current
Normal Operation
21μA
130μA
Sink Current
VUVLO < VUVLOTH
10mA /1.5A
Selectable in bit 0 of DEVICE_SETUP5 Register
VOVLO > VOVLOTH
10mA /1.5A
Selectable in bit 1 of DEVICE_SETUP5 Register
OC / FET Plim Fault
after Regulation Timer expiry
10mA /1.5A
Selectable in bit 4 of 
DEVICE_SETUP5 Register
x
Blanking Timer Expiry,
Device entering Current/Power 
limiting
x
10mA /1.5A
Selectable in bit 3 of 
DEVICE_SETUP5 Register
Digital Faults / Commands
(OT, FET_FAIL, Operation, Power 
Cycle, WD expiry)
10mA /1.5A
Selectable in bit 2 of DEVICE_SETUP5 Register
CB / SCP
1.5A
VIN < POR
Insertion Time
10mA
Max Regulation sink current
OC/FET Plim Limiting
235μA
x
7.4.3 Fault Timer and Restart
When current or power limit thresholds are exceeded during startup or other fault events, the device regulates 
GATE1 voltage to control load current and limit power dissipation in the primary FET (Q1). During these 
regulation time periods, a 75μA current source charges the external fault timer capacitor (CTMR) connected to 
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the TIMER pin and for LM5066H2 the GATE2 remains completely off. If the limiting condition resolves before 
the TIMER pin voltage reaches 3.9V, the device returns to normal operation and CTMR discharges through a 
10mA current sink. However, if TIMER pin voltage reaches 3.9V while still in limiting mode, GATE1 turns off 
through either a 10mA or 1.5A pulldown current. The subsequent restart behavior depends on the selected retry 
configuration.
With the RETRY pin high, the device latches GATE low after the fault timeout period. The timing capacitor then 
discharges to ground through a 2.5μA current sink. GATE remains low until a power up sequence is externally 
initiated by either cycling input voltage or momentarily pulling the UVLO/EN pin below its threshold using an 
open-collector or open-drain device. For successful restart, the TIMER pin voltage must be below 0.3V. While 
in this latched off condition, the TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register remains 
set.
Restart
Control
VIN
VIN
UVLO/EN
OVLO
GND
R1
R2
R3
Figure 7-4. Latched Fault Restart Control
The LM5066Hx features a configurable auto-retry mechanism for fault recovery. After a fault timeout period, the 
device initiates an automatic restart sequence where the TIMER pin cycles between 3.9V and 1.2V seven times. 
The duration of each cycle depends on the external timer capacitor (CTMR) value along with the internal 75μA 
charging current and 2.5μA discharge current. When the TIMER pin voltage reaches 0.3V during the eighth 
high-to-low transition, the device activates the 21μA current source at the GATE pin to turn on the external 
MOSFET (Q1). If the fault condition persists, the fault timeout period and restart sequence repeat according 
to the programmed retry settings. Basic retry behavior can be selected through the RETRY pin, which allows 
for either no retries (latched-off mode) or infinite retries. For more precise control, the DEVICE_SETUP register 
(D9h) enables selection of specific retry counts: 0, 1, 2, 4, 8, 16, or infinite. This programmability allows system 
designers to optimize fault recovery behavior based on application requirements. In The latched-off mode, the 
device keeps the FET in OFF state until OPERATION OFF command followed by OPERATION ON command is 
issued or UVLO/EN toggle or POWER_CYCLE command is issued or supply power cycle event occurs.
The timer discharge current is configurable to be 2.5μA or 75μA through bit 6 of the DEVICE_SETUP4 register. 
Retry delay timing can use either the analog fault timer with external capacitor or a digital timer, selectable via 
bits 2:3 of DEVICE_SETUP4. When using digital timing, the retry delay period is programmable from 10ms to 
10s using bits 4:7 of the DELAY_CONFIG register.
1.2 V
1
2
3
7
8
10mA / 1.5A pulldown
Fault
Detection
GATE
Pin
Load
Current
T
ILIMI
tRESTART
Fault Timeout
Period
21 
A
Gate Charge
2.5
A
3.9 V
75 
A
0.3 V
TIMER
Pin
Figure 7-5. Restart Sequence
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7.4.4 Shutdown Control
The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open 
collector or open-drain device, as shown in Figure 7-6. When UVLO/EN pin is released, the LM5066Hx switches 
on the FET with in-rush current and power limiting. The output may also be enabled or disabled by writing 80h or 
0h to the OPERATION (03h) register.
Shutdown 
Control
VIN
VIN
UVLO/EN
OVLO
GND
R1
R2
R3
Figure 7-6. Shutdown Control
7.4.5 Enabling/Disabling and Resetting
The LM5066Hx output can be disabled during normal operation by pulling the UVLO/EN pin below its threshold 
or the OVLO pin above its threshold, forcing the GATE voltage low with a pulldown strength of 10mA or 
1.5A. Toggling UVLO/EN also resets the device from a latched off state caused by exceeding the maximum 
retry count during overcurrent or overpower conditions. While UVLO/EN and OVLO pins control output state, 
they don't affect device memory. User programmed values for address, operation settings, and fault thresholds 
remain preserved in both operatnig memory and interal EEPROM regardless of these pins states. Output can 
also be controlled through the PMBus interface by writing 80h (enable) or 0h (disable) to the OPERATION 
register. After a fault condition, the device can be re-enabled by writing 0h followed by 80h to this register. The 
POWER_CYCLE command provides controlled output cycling, powering down and then up after a configurable 
delay set through the RETRY_CONFIG register.
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7.5 Programming
7.5.1 PMBus Command Support
The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error 
masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 
7-2.
Table 7-2. Supported PMBus Commands
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
1
01h
OPERATION
Retrieves or stores 
the operation status
Control
R/W
1
80h
No
2
03h
CLEAR_FAULTS
Clears the status 
registers and re-
arms the black box 
registers for updating
Control
Send 
byte
0
NA
No
3
10h
WRITE_PROTECT
Enable/Disable 
write protection 
for OPERATION, 
configuration 
registers, and 
EEPROM
Control
R/W
1
00h
Yes
4
12h
RESTORE_FACTORY_DEFAUL
TS
Initialize/Reset 
all configuration 
registers to their 
factory default values
Control
Send 
byte
0
NA
No
5
15h
STORE_USER_ALL
Store configuration 
values to internal 
EEPROM
Control
Send 
byte
0
NA
No
6
16h
RESTORE_USER _ALL
Initialize all 
configuration 
registers with the 
user programmed 
values stored in 
internal EEPROM
Control
Send 
byte
0
NA
No
7
19h
CAPABILITY
Supported PMBus® 
features
Telemetry
R
1
D0h
No
8
43h
VOUT_UV_WARN_LIMIT
Retrieves or stores 
output undervoltage 
warn limit threshold
Configuration
R/W
2
0000h
Yes
9
4Fh
OT_FAULT_LIMIT
Retrieves or stores 
over temperature 
fault limit threshold
Configuration
R/W
2
0FFFh 
(255°C)
Yes
10
51h
OT_WARN_LIMIT
Retrieves or stores 
over temperature 
warn limit threshold
Configuration
R/W
2
0FFFh 
(255°C)
Yes
11
57h
VIN_OV_WARN_LIMIT
Retrieves or stores 
input overvoltage 
warn limit threshold
Configuration
R/W
2
0FFFh
Yes
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Table 7-2. Supported PMBus Commands (continued)
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
12
58h
VIN_UV_WARN_LIMIT
Retrieves or stores 
input undervoltage 
warn limit threshold
Configuration
R/W
2
0000h
Yes
13
5Dh
IIN_OC_WARN_LIMIT
Retrieves or stores 
input current warn 
limit threshold (mirror 
at D3h, F8h)
Configuration
R/W
2
0FFFh
Yes
14
78h
STATUS_BYTE
Retrieves information 
about the parts 
operating status
Telemetry
R
1
01h
No
15
79h
STATUS_WORD
Retrieves information 
about the parts 
operating status
Telemetry
R
2
0801h
No
16
7Ah
STATUS_VOUT
Retrieves information 
about output voltage 
status
Telemetry
R
1
00h
No
17
7Ch
STATUS_INPUT
Retrieves information 
about input status
Telemetry
R
1
00h
No
18
7Dh
STATUS_TEMPERATURE
Retrieves information 
about temperature 
status
Telemetry
R
1
00h
No
19
7Eh
STATUS_CML
Communications, 
Memory,Logic status
Telemetry
R
1
00h
No
20
7Fh
STATUS_OTHER
Retrieves other status 
information
Telemetry
R
1
00h
No
21
80h
STATUS_MFR_SPECIFIC
Retrieves information 
about circuit breaker 
and MOSFET shorted 
status
Telemetry
R
1
10h
22
86h
READ_EIN
Retrieves energy 
meter measurement
Telemetry
Block 
Read
6
00h 00h 
00h 00h 
00h 00h
No
23
88h
READ_VIN
Retrieves input 
voltage measurement Telemetry
R
2
0000h
No
24
89h
READ_IIN
Retrieves input 
current measurement 
(Mirrors at D1h)
Telemetry
R
2
0000h
No
25
8Bh
READ_VOUT
Retrieves output 
voltage measurement Telemetry
R
2
0000h
No
26
8Ch
READ_IOUT
Retrieves output 
current measurement Telemetry
R
2
0000h
No
27
8Dh
READ_TEMPERATURE_1
Retrieves 
temperature 
measurement
Telemetry
R
2
0000h
No
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Table 7-2. Supported PMBus Commands (continued)
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
28
96h
READ_POUT
Retrieves output 
power measurement
Telemetry
R
2
0000h
No
29
97h
READ_PIN
Retrieves averaged 
input power 
measurement (mirror 
at DFh).
Telemetry
R
2
0000h
No
30
98h
PMBUS_Revision
PMBus® 
Specifications Part I 
and II rev 1.3
Telemetry
R
1
33h
No
31
99h
MFR_ID
Retrieves 
manufacturer ID in 
ASCII characters (TI)
Telemetry
Block 
Read
3
54h 49h 
0h
Metal
32
9Ah
MFR_MODEL
Retrieves part 
number in 
ASCII characters. 
(LM5066H)
Telemetry
Block 
Read
8
4Ch 4Dh 
35h 30h 
36h 36h 
48h 0h
Metal
33
9Bh
MFR_REVISION
Retrieves part 
revision letter or 
number in ASCII (for 
example, AA)
Telemetry
Block 
Read
2
41h 41h
Metal
34
A0h
READ_VIN_MIN
Minimum input 
voltage
Telemetry
R
2
0FFFh
No
35
A1h
READ_VIN_PEAK
Peak input voltage
Telemetry
R
2
0000h
No
36
A2h
READ_IIN_PEAK
Peak input current
Telemetry
R
2
0000h
No
37
A3h
MFR_SPECIFIC_05 
READ_PIN_PEAK
Retrieves measured 
peak input power 
measurement
Telemetry
R
2
0000h
No
38
A4h
READ_VOUT_MIN
Minimum output 
voltage
Telemetry
R
2
0FFFh
No
39
BCh
USER_DATA
General User 
programmable data
Configuration
R/W
1
00h
Yes
40
C7h
READ_TEMP_AVG
Average device 
temperature
Telemetry
R
2
0000h
No
41
C8h
READ_TEMP_PEAK
Peak device 
temperature
Telemetry
R
2
0000h
No
42
C9h
READ_SAMPLE_ BUF
ADC sample buffer
Telemetry
Block 
Read
64
0000h
No
43
CAh
POWER_CYCLE
Power down 
output and restart 
after a delay 
programmed through 
the RETRY_CONFIG 
register
Control
Send 
byte
0
Undefined
No
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Table 7-2. Supported PMBus Commands (continued)
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
44
CCh
DEVICE_SETUP1
Retrieves or stores 
information about 
number of retry 
attempts
Configuration
R/W
1
0000h
Yes
45
CDh
DEVICE_SETUP4
Device configuration
Configuration
R/W
1
91h
Yes
46
CEh
DEVICE_SETUP5
Device configuration
Configuration
R/W
1
00h
Yes
47
D0h
READ_VAUX
Retrieves auxiliary 
voltage measurement Telemetry
R
2
0000h
No
48
D1h
MFR_READ_IIN
Retrieves input 
current measurement 
(Mirror at 89h)
Telemetry
R
2
0000h
No
49
D2h
MFR_READ_PIN
Retrieves input power 
measurement
Telemetry
R
2
0000h
No
50
D3h
MFR_IIN_OC_WARN_LIMIT
Retrieves or stores 
input current limit 
warn threshold 
(Mirror at 5Dh, F8h)
Configuration
R/W
2
0FFFh
Yes
51
D4h
MFR_PIN_OP_WARN_LIMIT
Retrieves or stores 
input power limit warn 
threshold
Configuration
R/W
2
0FFFh
Yes
52
D6h
CLEAR_PIN_PEAK
Resets the contents 
of the peak input 
power register to 0
Control
Send 
byte
0
Undefined
No
53
D7h
GATE_MASK
Allows the user 
to disable MOSFET 
gate shutdown 
for various fault 
conditions
Configuration
R/W
1
42h
Yes
54
D8h
ALERT_MASK
Retrieves or stores 
user SMBA fault 
mask
Configuration
R/W
2
FD20h
Yes
55
D9h
READ_VAUX_AVG
Retrieves average 
Vaux measurement
Telemetry
R
2
0000h
No
56
DAh
BLOCK_READ
Retrieves most 
recent diagnostic and 
telemetry information 
in a single transaction
Telemetry
Block 
Read
12
0880h 
0000h 
0000h 
0000h 
0000h 
0000h
No
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Table 7-2. Supported PMBus Commands (continued)
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
57
DBh
SAMPLES_FOR_AVG
Exponent value 
AVGN for number 
of samples to be 
averaged (N = 
2AVGN), range = 00h 
to 0Ch
Configuration
R/W
1
08h
Yes
58
DCh
READ_AVG_VIN
Retrieves averaged 
input voltage 
measurement
Telemetry
R
2
0000h
No
59
DDh
READ_AVG_VOUT
Retrieves averaged 
output voltage 
measurement
Telemetry
R
2
0000h
No
60
DEh
READ_AVG_IIN
Retrieves averaged 
input current 
measurement
Telemetry
R
2
0000h
No
61
DFh
READ_AVG_PIN
Retrieves averaged 
input power 
measurement
Telemetry
R
2
0000h
No
62
E0h
BB_CLEAR
Clear 
READ_BB_RAM data Control
Send 
byte
0
Undefined
No
63
E1h
DIAGNOSTIC_WORD_READ
Manufacturer-specific 
parallel of the 
STATUS_WORD to 
convey all FAULT/
WARN data in a 
single transaction
Telemetry
R
2
0880h
No
64
E2h
AVG_BLOCK_READ
Retrieves most recent 
average telemetry 
and diagnostic 
information in a single 
transaction
Telemetry
Block 
Read
12
0880h 
0000h 
0000h 
0000h 
0000h 
0000h
No
65
E3h
BB_ERASE
Erase Blackbox data 
in internal EEPROM
Control
Send 
byte
0
Undefined
No
66
E4h
BB_CONFIG
Blackbox 
configuration
Configuration
R/W
1
00h
Yes
67
E5h
OC_BLANKING_TIMERS
Transient overcurrent 
blanking timer1 and 2 Configuration
R/W
1
75h
Yes
68
E7h
DELAY_CONFIG
Insertion and Retry 
delay for SOA Timer 
Profile
Configuration
R/W
1
84h
Yes
69
E8h
WD_PLB_ TIMER
WatchDog and Power 
Limit Blanking Timer 
Configuration
Configuration
R/W
1
BFh
Yes
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Table 7-2. Supported PMBus Commands (continued)
S.No.
Code
Name
Function
Type
R/W
No. of 
Data 
Bytes
Default 
Value
Stored in 
Internal 
EEPROM
70
E9h
PK_MIN_AVG
Peak/Min/Average 
configuration
Configuration
R/W
1
00h
Yes
71
EAh
P2t TIMER
P2t timer 
configuration
Configuration
R/W
1
0Ch
Yes
72
EBh
FETCH_BB_EEPROM
Fetch Blackbox 
EEPROM contents 
into internal shadow/
working registers
Control
Send 
byte
0
Undefined
No
73
ECh
READ_BB_RAM
Blackbox RAM/
working registers
Telemetry
Block 
Read
7
00h
Yes
74
EDh
ADC_CONFIG_1
ADC Configuration
Configuration
R/W
1
00h
Yes
75
EEh
ADC_CONFIG_2
ADC Configuration
Configuration
R/W
1
00h
Yes
76
EFh
DEVICE_SETUP2
Device configuration
Configuration
R/W
1
00h
Yes
77
F0h
DEVICE_SETUP3
Device configuration
Configuration
R/W
1
00h
Yes
78
F2h
IIN OFFSET CALIBRATION
Configure IIN offset
Configuration
R/W
1
00h
Yes
79
F3h
STATUS_MFR_SPECIFIC_2
Additional 
manufacturer specific 
fault status
Telemetry
R
2
0000h
No
80
F4h
READ_BB_EEPROM
Blackbox EEPROM 
content
Telemetry
Block 
Read
16
Undefined
No
81
F6h
BB_TIMER
Blackbox tick timer
Telemetry
R
1
00h
No
82
F7h
PMBUS_ADDR
Device address for 
ADR0 = ADR1 = 
ADR2 = Open setting
Configuration
R/W
1
40h
Yes
83
F8h
OC_WARN_LIMIT
Retrieves or stores 
input current warn 
limit threshold (mirror 
at 5Dh, F8h)
Configuration
R/W
2
0FFFh
Yes
7.5.2 Detailed Descriptions of PMBus Commands
7.5.2.1 OPERATION (01h, Read/Write Byte)
The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command 
can be used to switch the MOSFET ON and OFF under host control. It is also used to re-enable the MOSFET 
after a fault triggered shutdown. Writing an OFF command, followed by an ON command after the fault condition 
is cleared, clears all faults and warning bits in the status registers and re-enables the device. Writing only an 
ON command after a fault-triggered shutdown does not clear the fault registers or re-enable the device. The 
OPERATION command is issued with the write byte protocol.
Table 7-3. Recognized OPERATION Command Values
Name
Description
Default
80h
Switch ON
80h
00h
Switch OFF
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7.5.2.2 CLEAR_FAULTS (03h, Send Byte)
The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags 
and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, 
the SMBA signal may not clear or re-asserts almost immediately. Issuing a CLEAR_FAULTS command does 
not cause the MOSFET to switch back on in the event of a fault turnoff; that must be done by issuing an 
OPERATION OFF command followed by OPERATION ON command or a POWER_CYCLE command after the 
fault condition is cleared, or through an auto-retry sequence. This command also clears the BB_RAM contents 
and resets the BB_TIMER register to zero (0). This command has no effect on Blackbox EEPROM memory 
contents. This command uses the PMBus send byte protocol. There is no data byte for this command. This 
command is write only.
Note
TI recommends sending the CLEAR_FAULTS command after every successful power-up of the 
device to clear the warning and fault bits set in the status registers during initialization, if any. This also 
ensures the SMBA is de-asserted.
7.5.2.3 WRITE_PROTECT (10h, Read/Write Byte)
The WRITE_PROTECT command is a standard PMBus command used to control writing to the PMBus device. 
The intent of this command is to provide protection against accidental changes. This command is not intended to 
provide protection against deliberate or malicious changes to a device’s configuration or operation. All supported 
commands may have their parameters read, regardless of the WRITE_PROTECT settings. Commands with 
write disabled by WRITE_PROTECT shall be treated as Read Only. If an attempt is made to write to a command 
that is WRITE PROTECTED the device shall treat this as invalid data, declare a communications fault.
This command has one data byte, as described in table below.
Table 7-4. WRITE_PROTECT Register Description
Data Byte Value
Meaning
Default
1000 0000
Disable all writes except to the 
WRITE_PROTECT command
0000 0000
0100 0000
Disable all writes except to the 
WRITE_PROTECT, OPERATION commands
0010 0000
0000 0011
Disable all writes, and need VDD/VIN recycle 
to unlock
0000 0010
Permanent disable all writes
The device remains unlocked until this 
byte is stored in internal EEPROM using 
the STORE_USER_ALL command followed 
by RESTORE_USER_ALL command in 
conjunction with the DEVICE_SETUP1 bit 1 
setting.
0000 0001
Reserved
0000 0000
Enable writes to all commands.
7.5.2.4 RESTORE_FACTORY_DEFAULTS (12h, Send Byte)
RESTORE_FACTORY_DEFAULTS is a standard PMBus command that initializes or resets all the operating 
memory registers to their hardware defaults. This command uses the PMBus send byte protocol. This command 
is write only and has no data byte.
7.5.2.5 STORE_USER_ALL (15h, Send Byte)
STORE_USER_ALL is a standard PMBus command that writes the contents of the operating memory to their 
respective internal EEPROM configuration memory.
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This command uses the PMBus send byte protocol. This command is write only and has no data byte.
7.5.2.6 RESTORE_USER_ALL (16h, Send Byte)
RESTORE_USER_ALL is a standard PMBus command that copies the configuration registers of the internal 
EEPROM memory to the matching locations in the operating memory.
This command uses the PMBus send byte protocol. This command is write only and has no data byte.
7.5.2.7 CAPABILITY (19h, Read Byte)
The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions 
supported by the LM5066Hx. This command is read with the PMBus read byte protocol.
Table 7-5. CAPABILITY Register Description
Bit
Name
Value
Description
Default
7
PEC Support
Packet Error Correction 
(PEC) support
1
PEC supported
1
0
PEC not supported
6:5
Bus Speed
Maximum bus interface 
speed
00
100kHz
10
01
400kHz
10
1MHz
11
Reserved for future use
4
SMBA/ARA
SMB Alert/Alert Response 
Address support
1
SMBA/ARA supported
1
0
SMBA/ARA not supported
3:0
Reserved
0000
Reserved
0000
7.5.2.8 VOUT_UV_WARN_LIMIT (43h, Read/Write Word)
The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the 
threshold for the VOUT undervoltage warning detection. Reading and writing to this register should use the 
coefficients shown in Table 7-72. Accesses to this command should use the PMBus read or write word protocol. 
If the measured value of VOUT falls below the value in this register, VOUT_UV_WARN flags are set and the 
SMBA signal is asserted. The warning flag and associated alert signal will be cleared after the output voltage 
recovers to a level above the VOUT_UV_WARN threshold and the CLEAR_FAULTS command is issued.
Table 7-6. VOUT_UV_WARN_LIMIT Register
Bit
Name
Description
Minimum Value
Maximum Value
Default
0
VOUT_UV_WARN_LIMIT
Outupt Undervoltage 
warning threshold
0x0000h (0V)
0x0FFFh (89.1V)
0x0000h (0V)
When an output undervoltage warning is detected, the device:
•
sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register
•
sets the OUT_STATUS bit in the upper byte of the STATUS_WORD register
•
sets the VOUT_UV_WARN bit in the STATUS_OUT register
•
notifies the host by asserting SMBA, if it is not masked setting the STATUS_OUT bit in the ALERT_MASK 
register
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7.5.2.9 OT_FAULT_LIMIT (4Fh, Read/Write Word)
The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the 
threshold for the overtemperature fault detection. Reading and writing to this register should use the coefficients 
shown in Table 7-72. Accesses to this command should use the PMBus read or write word protocol. If the 
measured temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched 
off, OT FAULT flags set, and the SMBA signal asserted. After the measured temperature falls below the value 
in this register, the MOSFET may be switched back on with the OPERATION OFF command followed by 
OPERATION ON command or a POWER_CYCLE command after the fault condition is cleared, or through an 
auto-retry sequence.
Table 7-7. OT_FAULT_LIMIT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
OT_FAULT_LIMIT
Device 
overtemperature fault 
threshold
0x0000h (-256 ºC)
0x01FFh (255 ºC)
0x0FFFh (255ºC)
7.5.2.10 OT_WARN_LIMIT (51h, Read/Write Word)
The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the 
threshold for the over-temperature warning detection. Reading and writing to this register should use the 
coefficients shown in Table 7-72. Accesses to this command should use the PMBus read or write word protocol. 
If the measured temperature exceeds this value, an over-temperature warning is triggered and the OT WARN 
flags set in the respective registers and the SMBA signal asserted.
Table 7-8. OT_WARN Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
OT_WARN_LIMIT
Device 
overtemperature 
warning threshold
0x0000h (-256ºC)
0x01FFh (255ºC)
0x0FFFh (255ºC)
7.5.2.11 VIN_OV_WARN_LIMIT (57h, Read/Write Word)
The VIN_OV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the 
threshold for the VIN overvoltage warning detection. Reading and writing to this register should use the 
coefficients shown in Table 7-72. Accesses to this command should use the PMBus read or write word protocol. 
If the measured value of VIN rises above the value in this register, VIN_OV_WARN flags are set in the 
respective registers and the SMBA signal is asserted.
Table 7-9. VIN_OV_WARN_LIMIT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
VIN_OV_WARN_LIMI
T
Input overvoltage 
warning threshold
0x0000 (0V)
0x0FFF (89.1V)
0x0FFF (89.1V)
7.5.2.12 IIN_OC_WARN_LIMIT (5Dh, Read/Write Word)
The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input overcurrent warning threshold. In the event 
that the input current rises above the value set in this register, the IIN overcurrent flags are set in the respective 
registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus read/
write word protocol. Reading and writing to this register should use the coefficients shown in Table 7-72. This 
value is also mirrored at (D3h, F8h).
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Table 7-10. IIN_OC_WARN_LIMIT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
IIN_OC_WARN_LIMI
T
Input overcurrent 
warning threshold
0x0000h (0A)
0x0FFFh (1.08xVCL/
RSNS A)
0x0FFFh (1.08xVCL/
RSNS A)
7.5.2.13 STATUS_BYTE (78h, Read Byte)
The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the 
state of the LM5066Hx. Accesses to this command should use the PMBus read byte protocol. To clear bits in this 
register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued.
Table 7-11. STATUS_BYTE Register Description
Bit
Name
Value
Description
Default
7
Reserved
0
Reserved
0
6
OFF
FET drive status
1
FET gate driver disabled
0
0
FET gate drive enabled
5:4
Reserved
00
Reserved
00
3
VIN_UV_FLT
VIN undervoltage
1
VIN UV fault detected
0
0
VIN UV fault not detected
2
STATUS_TEMP
Overtemperature fault
1
Active bits set in 
STATUS_TEMPERATURE 
register
0
0
No active bits set in 
STATUS_TEMPERATURE 
register
1
CML_ERR
Communication, Memory 
or Logic error
1
Active bits set in 
STATUS_CML register
0
0
No active bits set in 
STATUS_CML register
0
NONE_OF_THE_ABOVE
1
An event other than the 
ones listed in bits 7:1 has 
occurred
1
0
An event other than the 
ones listed in bits 7:1 has 
not occurred
7.5.2.14 STATUS_WORD (79h, Read Word)
The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags 
indicating the state of the LM5066Hx. Accesses to this command should use the PMBus read word protocol. 
To clear bits in this register, the underlying fault should be removed and a CLEAR _FAULTS command issued. 
The INPUT and VIN UV flags default to 1 on startup; however, they are cleared to 0 after the first time the input 
voltage exceeds the resistor-programmed UVLO threshold.
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STATUS_WORD (79h)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OUT_STATUS
RESERVED
INPUT_STATUS
FET_FAIL
UNKNOWN
RESERVED
PGOODB
CB_FAULT
UNKNOWN
CML_ERR
TEMP_FLT
VIN_UV_FLT
BUSY
RESERVED
RESERVED
FET_OFF
High Byte
Low Byte [STATUS_BYTE (78h)]
STATUS_CML 
Register (7Eh)
STATUS_MFR_
SPECIFIC_2 
Register (F3h)
STATUS_OUT 
Register (7Ah)
STATUS_MFR_
SPECIFIC 
Register (80h)
STATUS_TEMP 
Register (7Dh)
STATUS_INPUT 
Register (7Ch)
Figure 7-7. Status Register Bit Map
Table 7-12. STATUS_WORD Register Description
Bit
Name
Value
Description
Default
15
OUT_STATUS
OUTPUT fault status
1
Active bits set in the 
STATUS_OUT register
0
0
No active bits set in the 
STATUS_OUT register
14
Reserved
0
Reserved
0
13
INPUT_STATUS
INPUT fault status
1
Active bits set in the 
STATUS_INPUT register
0
0
No active bits set in the 
STATUS_INPUT register
12
FET_FAIL
FET Fail status
1
FET fail detected
0
0
No FET fail detected
11
PGOODB
Power Good status
1
PGOOD de-asserted
1
0
PGOOD asserted
10
Reserved
0
Reserved
0
9
CB_FAULT
Circuit breaker fault 
asserted
1
Circuit breaker fault 
triggered
0
0
No Circuit breaker fault 
triggered
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Table 7-12. STATUS_WORD Register Description (continued)
Bit
Name
Value
Description
Default
8
UNKNOWN
1
An event other than the 
ones listed in bits 15:1 has 
occurred
0
0
An event other than the 
ones listed in bits 15:1 has 
not occurred
7:0
Same as STATUS_BYTE register
7.5.2.15 STATUS_VOUT (7Ah, Read Byte)
The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV warn flag. 
Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying 
fault should be cleared and a CLEAR_FAULTS command issued.
Table 7-13. STATUS_VOUT Register Description
Bit
Name
Value
Description
Default
7:6
Reserved
00
Reserved
00
5
VOUT_UV_WARN
VOUT undervoltage 
warning
1
VOUT UV warning 
occurred
0
0
VOUT UV warning 
occurred
4:0
Reserved
00
Reserved
00
7.5.2.16 STATUS_INPUT (7Ch, Read Byte)
The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags 
related to input voltage, current, and power. Accesses to this command should use the PMBus read byte 
protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command 
issued.
Table 7-14. STATUS_INPUT Register Description
Bit
Name
Value
Description
Default
7
VIN_OV_FLT
VIN overvoltage fault
1
VIN OV fault has occurred
0
0
VIN OV fault has not occurred
6
VIN_OV_WARN
VIN overvoltage warning
1
VIN OV warning has occurred
0
0
VIN OV warning has not occurred
5
VIN_UV_WARN
VIN undervoltage warning
1
VIN UV warning has occurred
0
0
VIN UV warning has not occurred
4
VIN_UV_FLT
VIN undervoltage fault
1
VIN UV fault has occurred
0
0
VIN UV fault has not occurred
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Table 7-14. STATUS_INPUT Register Description (continued)
Bit
Name
Value
Description
Default
3
Reserved
0
Reserved
0
2
OC_FLT
Regulation TIMER expiry due to overcurrent 
in steady-state
1
Input overcurrent fault has occured
0
0
Input overcurrent fault has not occured
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Table 7-14. STATUS_INPUT Register Description (continued)
Bit
Name
Value
Description
Default
1
OC_WARN
Overcurrent warning
1
Input current crossed overcurrent warning 
threshold
0
0
Input current below overcurrent warning 
threshold
0
IN_OP_WARN
Overpower warning
1
Input power crossed overpower warning 
threshold
0
0
Input power has not crossed overpower 
warning threshold
7.5.2.17 STATUS_TEMPERATURE (7Dh, Read Byte)
The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags 
related to the temperature telemetry value. Accesses to this command should use the PMBus read byte protocol. 
To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued.
Table 7-15. STATUS_TEMP Register Description
Bit
Name
Value
Description
Default
7
OT_FLT
Overtemperature fault
1
Device temperature 
crossed overtemperature 
fault threshold
0
0
Device temperature below 
overtemperature fault 
threshold
6
OT_WARN
Overtemperature warning
1
Device temperature 
crossed overtemperature 
warning threshold
0
0
Device temperature below 
overtemperature warning 
threshold
5:0
Reserved
000000
Reserved
000000
7.5.2.18 STATUS_CML (7Eh, Read Byte)
The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to 
communication faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this 
register, a CLEAR_FAULTS command should be issued.
Table 7-16. STATUS_CML Register Description
Bit
Name
Value
Description
Default
7
INV_CMD
Command status
1
Invalid/unsupported 
command received
0
0
Valid/supported command 
received
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Table 7-16. STATUS_CML Register Description (continued)
Bit
Name
Value
Description
Default
6
INV_DATA
Data status
1
Invalid/unsupported data 
received
0
0
Valid/supported data 
received
5
INV_PEC
Packet Error Check status
1
PEC failed
0
0
PEC passed
4
MEMORY_FLT
Memory fault status
1
Memory related fault 
- Configuration Memory 
Content Invalid (Empty 
or corrupted) or 
STORE_USER_ALL or 
RESTORE_USER_ALL 
commands unsuccessful
0
0
No memory related fault
3:2
Reserved
000
Reserved
000
1
NONE_OF_ABOVE
1
A communication fault 
other than the ones listed 
in the table has occurred
0
0
A communication fault 
other than the ones listed 
in the table has not 
occurred
0
Reserved
0
Reserved
0
7.5.2.19 STATUS_OTHER (7Fh, Read Byte)
The STATUS_OTHER is a standard PMBus command that returns the value of a number of other flags 
indicating the state of the LM5066Hx. Accesses to this command should use the PMBus read byte protocol. 
To clear bits in this register, the underlying fault should be removed on the system and a CLEAR_FAULTS 
command issued.
Table 7-17. STATUS_VOUT Register Description
Bit
Name
Value
Description
Default
7:6
Reserved
00
Reserved
00
5
CB_FAULT
Circuit breaker fault 
asserted
1
Circuit breaker fault 
triggered
0
0
No Circuit breaker fault 
triggered
4:1
Reserved
0000
Reserved
0000
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Table 7-17. STATUS_VOUT Register Description (continued)
Bit
Name
Value
Description
Default
0
First to assert SMBA
First to assert SMBA
1
This device is the first one 
to assert SMBA
0
0
This device is not the first 
one to assert SMBA
7.5.2.20 STATUS_MFR_SPECIFIC (80h)
The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific 
status information. Accesses to this command should use the PMBus read byte protocol. To clear bits in this 
register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued.
Table 7-18. STATUS_MFR_SPECIFIC Register Description
Bit
Name
Value
Description
Default
7
CB_FAULT
Circuit breaker fault asserted
1
Circuit breaker fault triggered
0
0
No Circuit breaker fault triggered
6
FET_FAIL
FET Fail status
1
FET fail detected
0
0
No FET fail detected
5
Reserved
0
Reserved
0
4
DEFAULTS_LOADED
Defaults loaded status
1
Defaults loaded from internal EEPROM
1
0
No fault or warning detected
3
BB_RAM_FULL
BB RAM fill status
1
Seven (7) events have been recorded
0
0
Seven (7) events not yet recorded
2
FET_FAULT_GATE2
FET Fail type
0
1
FET fault detected at GATE2
0
No FET fault detected at GATE2
1
FET_FAULT_GATE1
FET Fail type
0
1
FET fault detected at GATE1
0
No FET fault detected at GATE1
0
FET_FAULT_DRAIN
FET Fail type
0
1
FET DRAIN fault detected
0
No FET DRAIN fault detected
The DEFAULTS_LOADED bit in the STATUS_MFR_SPECIFIC register is set when default configuration 
settings and thresholds are successfully loaded into the working registers either during startup or after a 
RESTORE_USER_ALL command, and this bit remains set until a CLEAR_FAULTS command is received.
7.5.2.21 READ_EIN (86h, Block Read)
The READ_EIN command is a standard PMBus® command which returns information to the host for computing 
the accumulated energy and average power consumption by a system powered by the eFuse. The information 
provided by this command is independent of any device specific averaging period, sampling frequency, or 
calculation algorithm.
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This command uses the PMBus® block read protocol with a block size of six (6).
This command returns six (6) bytes of data. The first two (2) bytes are the two's complement and signed 
output of an accumulator that continuously sums samples of the instantaneous input power (the product of the 
samples of the input voltage and input current). These two data bytes are encoded in the DIRECT format as 
described in Table 7-72. The accumulator values are scaled so that the units are in “watt-samples”. This value in 
“watt-samples” must be multiplied by the effective ADC sampling period to obtain the real world value of energy 
accumulation in joules.
The third data byte, ROLLOVER_COUNT is a count of rollover events for the accumulator. This byte is an 
unsigned integer indicating the number of times the accumulator has rolled over from its maximum positive value 
of 7FFFh to zero. The ROLLOVER_COUNT will periodically roll over from its maximum positive value to zero. It 
is up to the host to keep track of the state of the ROLLOVER_COUNT and account for the rollovers.
The other three (3) data bytes are a 24-bit unsigned integer that counts the number of samples of the 
instantaneous input power accumulated till now. This value will also roll over periodically from its maximum 
positive value to zero.
The combination of the accumulator and the rollover count may overflow within a few seconds. It is left to the 
host software to detect this overflow and handle it appropriately. Similarly, the sample count value will overflow.
Table 7-19. READ_EIN Register Description
Byte
Description
Default
0
Power Accumulator Low Byte
0x00
1
Power Accumulator High Byte
0x00
2
Power Accumulator Rollover Count
0x00
3
Sample Count Low byte
0x00
4
Sample Count Mid byte
0x00
5
Sample Count High byte
0x00
The host uses the accumulator value and rollover count to calculate the current “energy count” in “watt-samples” 
using Equation 1.
Energy_Count = Rollover_Count × Accumulator_Roll_Over_Value + Accumulator_Value 
(1)
Where the Accumulator_Roll_Over_Value is the maximum possible positive value of the accumulator plus one 
(1). It is necessary to add one (1) to the maximum accumulator value to make the average power calculation 
correctly. The Accumulator_Roll_Over_Value is calculated using Equation 2.
Accumulator_Roll_Over_Value = 1
m
YMAX + 1 × 10−R −b = 1
m
215 × 10−R −b
(2)
Table 7-72 includes the "m, b, R" coefficients used in Equation 2. Accumulator_Value is obtained using the 
coefficients in Table 7-72 and Equation 6. The real world value of energy accumulation in joules is calculated 
using Equation 3.
Accumulated_Energy = Energy_Count × Effective_ADC_Sampling_Period
(3)
The host calculates the average power in watt since the last reading using Equation 4.
Average_Power = Current_Energy_Count −Last_Energy_Count
Current_Sample_Count −Last_Sample_Count
(4)
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7.5.2.22 READ_VIN (88h, Read Word)
The READ_VIN command is a standard PMBus command that returns the 12-bit measured value of the input 
voltage. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is also used internally for the VIN overvoltage and undervoltage 
warning detection.
Table 7-20. READ_VIN Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VIN
Value measured for input 
voltage
0x0000 (0V)
0x0FFF (89.1V)
7.5.2.23 READ_IIN (89h, Read Word)
The READ_IIN command is a standard PMBus command that returns the 12-bit measured value of the input 
current. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is also mirrored at (D1h).
Table 7-21. READ_IIN Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_IIN
Value measured for 
input current
0x0000 (0A)
0x0FFF 
(1.08xVCL/RSNS 
A)
0x0000 (0A)
0x0FFF 
(2.16xVCL/RSNS 
A)
7.5.2.24 READ_VOUT (8Bh, Read Word)
The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the 
output voltage. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command 
should use the PMBus read word protocol. This value is also used internally for the VOUT undervoltage warning 
detection.
Table 7-22. READ_VOUT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VOUT
Value measured for output 
voltage
0x0000 (0V)
0x0FFF (89.1V)
7.5.2.25 READ_IOUT (8Ch, Read Word)
The READ_IOUT command is a standard PMBus command that returns the 12-bit measured value of the input 
current. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is same as READ_IIN (89h).
Table 7-23. READ_IOUT Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_IOUT
Value measured for 
input current
0x0000 (0A)
0x0FFF 
(1.08xVCL/RSNS 
A)
0x0000 (0A)
0x0FFF 
(2.16xVCL/RSNS 
A)
7.5.2.26 READ_TEMPERATURE_1 (8Dh, Read Word)
The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of 
the temperature measured by the external temperature sense diode. Reading this register should use the 
coefficients shown in Table 7-72. Accesses to this command should use the PMBus read word protocol. This 
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value is also used internally for the overtemperature fault and warning detection. This data has a range of 
–256°C to 255°C after the coefficients are applied.
Table 7-24. READ_TEMPERATURE_1 Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_TEMPERATURE_
1
Measured value for 
TEMPERATURE
0x0000 (-256°C)
0x01FF (255°C)
7.5.2.27 READ_POUT (96h, Read Word)
The READ_POUT command is a standard PMBus command that returns the 12-bit measured value of the input 
power. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol.
Table 7-25. READ_POUT Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_POUT
Value measured for 
input power
0x0000 (0W)
0x0FFF 
(96.23xVCL/RSNS 
W)
0x0000 (0W)
0x0FFF 
(192.45xVCL/RSNS 
W)
7.5.2.28 READ_PIN (97h, Read Word)
The READ_PIN command is a standard PMBus command that returns the 12-bit measured value of the input 
power. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is also mirrored at (D2h).
Table 7-26. READ_PIN Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_PIN
Value measured for 
input power
0x0000 (0W)
0x0FFF 
(96.23xVCL/RSNS 
W)
0x0000 (0W)
0x0FFF 
(192.45xVCL/RSNS 
W)
7.5.2.29 PMBUS_REVISION (98h, Read Byte)
PMBUS_REVISION is a standard PMBus command which returns the revision of the PMBus standard to which 
the device conforms.
The command has one data byte. Bits[7:4] indicate the revision of PMBus specification Part I to which the device 
is compliant. Bits[3:0] indicate the revision of PMBus specification Part II to which the device is compliant. To 
access this command, use the PMBus read byte protocol.
This command returns 0x33h from the LM5066Hx hotswap. This implies the device is compliant with Part I rev 
1.3 and Part II rev 1.3.
7.5.2.30 MFR_ID (99h, Block Read)
The MFR_ID command is a standard PMBus command that returns the identification of the manufacturer. To 
read the MFR_ID, use the PMBus block read protocol.
Table 7-27. MFR_ID Register
Byte
Name
Value
1
MFR ID-1
54h ‘T’
2
MFR ID-2
49h ‘I’
3
MFR ID-3
00h
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7.5.2.31 MFR_MODEL (9Ah, Block Read)
The MFR_MODEL command is a standard PMBus command that returns the part number of the chip. To read 
the MFR_MODEL, use the PMBus block read protocol.
Table 7-28. MFR_MODEL Register
Byte
Name
Value
1
MFR ID-1
4Ch ‘L’
2
MFR ID-2
4Dh ‘M’
3
MFR ID-3
35h ‘5’
4
MFR ID-4
30h ‘0’
5
MFR ID-5
36h ‘6’
6
MFR ID-6
36h ‘6’
7
MFR ID-7
48h 'H'
8
MFR ID-8
00h
7.5.2.32 MFR_REVISION (9Bh, Block Read)
The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To 
read the MFR_REVISION, use the PMBus block read protocol.
Table 7-29. MFR_REVISION Register
Byte
Name
Value
1
MFR ID-1
41h ‘A’
2
MFR ID-2
41h ‘A’
7.5.2.33 USER_DATA (BCh, Read/Write Byte)
This register is provided for user application purposes. Any value written to this register can be read back. The 
value has no impact on the internal operation or configuration of the chip.
Table 7-30. USER_DATA Register
Bit
Name
Default
7:0
USER_DATA
0x00h
7.5.2.34 READ_VIN_MIN (A0h, Read Word)
The READ_VIN_MIN command is a standard PMBus command that returns the 12-bit minimum input voltage 
measured since a power-on reset or the last RESET_MIN (Bit[5] in the PK_MIN_AVG register) made high. 
Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should use the 
PMBus read word protocol.
Table 7-31. READ_VIN_MIN Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
READ_VIN_MIN
Value measured 
for minimum input 
voltage since reset or 
last clear
0x0000 (0V)
0x0FFF (89.1V)
0x0FFF (89.1V)
7.5.2.35 READ_VIN_PEAK (A1h, Read Word)
The READ_VIN_PEAK command is a standard PMBus command that returns the 12-bit peak input voltage 
measured since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high. 
Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should use the 
PMBus read word protocol.
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Table 7-32. READ_VIN_PEAK Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
READ_VIN_PEAK
Value measured for 
peak input voltage 
since reset or last 
clear
0x0000 (0V)
0x0FFF (89.1V)
0x0000 (0V)
7.5.2.36 READ_IIN_PEAK (A2h, Read Word)
The READ_IIN_PEAK command is a standard PMBus command that returns the 12-bit peak input current 
measured since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high. 
Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should use the 
PMBus read word protocol.
Table 7-33. READ_IIN_PEAK Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_IIN_PEAK
Value measured for 
maximum input current 
since reset or last clear
0x0000 (0A)
0x0FFF 
(1.08xVCL/RSNS 
A)
0x0000 (0A)
0x0FFF 
(2.16xVCL/RSNS 
A)
7.5.2.37 READ_PIN_PEAK (A3h)
The READ_PIN_PEAK command reports the maximum input power measured since a power-on reset or the last 
CLEAR_PIN_PEAK command or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG (E9h) register) made high. 
To access the READ_PIN_PEAK command, use the PMBus read word protocol. Use the coefficients shown in 
Table 7-72.
Table 7-34. READ_PIN_PEAK Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_PIN_PEAK
Value measured for maximum 
input power since reset or last 
clear
0x0000 (0W)
0x0FFF (96.23xVCL/RSNS W)
7.5.2.38 READ_VOUT_MIN (A4h, Read Word)
The READ_VOUT_MIN command is a standard PMBus command that returns the 12-bit minimum input voltage 
measured since a power-on reset or the last RESET_MIN (Bit[5] in the PK_MIN_AVG register) made high. 
Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should use the 
PMBus read word protocol. This value is also used internally for the VOUT undervoltage warning detection.
Table 7-35. READ_VOUT_MIN Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default
15:0
READ_VOUT_MIN
Value measured 
for minimum output 
voltage since reset or 
last clear
0x0000 (0V)
0x0FFF (89.1V)
0x0FFF (89.1V)
7.5.2.39 READ_TEMP_AVG (C7h, Read Word)
The READ_TEMP_AVG command reports the 12-bit ADC measured average of the signed temperature value 
from the external temperature sense diode. Average count can be programmed through SAMPLES_FOR_AVG 
register. The contents of READ_TEMP_AVG register can be reset to zero (0x0000h) by setting Bit[6] in 
the PK_MIN_AVG register high. Reading this register should use the coefficients shown in Table 7-72. This 
command uses the PMBus read word protocol.
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Table 7-36. READ_TEMP_AVG Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_TEMP_AVG
Value measured for 
average temperature since 
reset or last clear
0x0000 (-256°C)
0x01FF (255°C)
7.5.2.40 READ_TEMP_PEAK (C8h, Read Word)
The READ_TEMP_PEAK command is a standard PMBus command that returns the signed value of 
the temperature measured by the external temperature sense diode since a power-on reset or the last 
RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high. Reading this register should use the coefficients 
shown in Table 7-72. Accesses to this command should use the PMBus read word protocol. This value is also 
used internally for the overtemperature fault and warning detection. This data has a range of –256°C to 255°C 
after the coefficients are applied.
Table 7-37. READ_TEMP_PEAK Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_TEMP_PEAK
Measured value for peak 
TEMPERATURE since 
reset or last clear
0x0000 (-256°C)
0x01FF (255°C)
7.5.2.41 READ_SAMPLE_BUF (C9h, Block Read)
READ_SAMPLE_BUF is a manufacturer-specific command used to read the latest sixty-four (64) samples of 
a particular parameter from a round-robin ADC buffer available in the device RAM. This allows multiple ADC 
samples to be captured at a higher speed and read out at on go without the bottleneck of reading individual 
samples sequentially over the PMBus serial interface. This allows the system designer to reconstruct the time 
domain profile/waveform of that parameter in a given time interval. This could be useful during design or system 
debugging by functioning like an in-built "digital oscilloscope". The rate at which ADC samples are updated 
in the buffer depends on the effective ADC sampling period and the decimation rate/sample skip count. The 
ADC channel to sample for buffering and the decimation rate/sample skip count can be configured through 
the ADC_CONFIG_2 register. By selecting different decimation rates, users can choose between “fine time 
resolution with short aperture” and “coarse time resolution with wide aperture”.
This command uses the PMBus block read protocol with a block size of sixty-four (64).
Follow the PMBus DIRECT format conversion using the coefficients in Table 7-72, bytes into their real-world 
values in the appropriate unit.
The ADC sample buffer starts buffering as soon as the device powers up. The buffering is paused under two 
different conditions:
1.
The instant READ_SAMPLE_BUF command is issued. This ensures the sample buffer is not overwritten 
with new values while the host is reading out the previous set of values. After sixty-four (64) bytes have been 
read, it will again start buffering new samples.
2.
In the event of a fault, sample buffer data is latched internally. This ensures the snapshot of the samples 
prior to the fault event is preserved even if there's a delay from host in reading out the sample buffer. After 
issuing the CLEAR_FAULTS command, or writing OPERATION OFF command followed by OPERATION 
ON command, or toggling the EN/UVLO pin, it will again start buffering new samples.
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0
1
2
63
0
1
2
. . . .
Skip count = 0
. . . .
63
12-bits
0
1
2
3
4
5
6
0
1
2
. . . .
. . . .
Skip count = 2
Skip count = 2
. . . .
63
12-bits
Skip count = 2
Skip count = 2
. . . .
64
12-bits
ADC raw output
187
188
189
190
191
192
ADC
fS
ADC
fS
12-bits
ADC raw output
ADC sample buffer
PMBus Block Read
ADC sample buffer
PMBus Block Read
Figure 7-8. ADC Sample Buffering Example
7.5.2.42 POWER_CYCLE (CAh, Send Byte)
POWER_CYCLE is a manufacturer specific command used to power down the output and power ON after 
a delay. The delay can be configured using bits (7:4) of DELAY_CONFIG register register. Execution of this 
command initiates a Power Path reset.
This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is 
write only.
Note
If the device is turned OFF due a fault, issuing a POWER_CYCLE command alone doesn't alter the 
state of the device. This command should be preceded by a CLEAR_FAULTS command.
7.5.2.43 READ_VAUX (D0h, Read Word)
The READ_VAUX command reports the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal 
to 2.97 V to ground are reported at plus full scale (0FFFh). Voltages less than or equal to 0 V referenced to 
ground are reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus read word 
protocol.
Table 7-38. READ_VAUX Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VAUX
Value measured for 
auxiliary voltage source 
connected at the VAUX 
pin
0x0000 (0V)
0x0FFF (2.97V)
7.5.2.44 MFR_READ_IIN (D1h, Read Word)
The MFR_READ_IIN command is a PMBus command that returns the 12-bit measured value of the input 
current. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is also mirrored at (89h).
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Table 7-39. READ_IIN Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
MFR_READ_IIN
Value measured for 
input current
0x0000 (0A)
0x0FFF 
(1.08xVCL/RSNS 
A)
0x0000 (0A)
0x0FFF 
(2.16xVCL/RSNS 
A)
7.5.2.45 MFR_READ_PIN (D2h)
The MFR_READ_PIN command is a PMBus command that returns the 12-bit measured value of the input 
power. Reading this register should use the coefficients shown in Table 7-72. Accesses to this command should 
use the PMBus read word protocol. This value is also mirrored at (97h).
Table 7-40. READ_PIN Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
MFR_READ_PI
N
Value measured for 
input power
0x0000 (0W)
0x0FFF 
(96.23xVCL/RSNS 
W)
0x0000 (0W)
0x0FFF 
(192.45xVCL/RSNS 
W)
7.5.2.46 MFR_IIN_OC_WARN_LIMIT (D3h, F8h, Read/Write Word)
The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input overcurrent warning threshold. In the event 
that the input current rises above the value set in this register, the IIN overcurrent flags are set in the respective 
registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus read/
write word protocol. Reading and writing to this register should use the coefficients shown in Table 7-72. This 
value is also mirrored at (5Dh, F8h).
Table 7-41. MFR_IIN_OC_WARN_LIMIT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default Value
15:0
MFR_IIN_OC_WARN
_LIMIT
Input overcurrent 
warning threshold
0x0000h (0A)
0x0FFFh (1.08xVCL/
RSNS A)
0x0FFFh (1.08xVCL/
RSNS A)
7.5.2.47 MFR_PIN_OP_WARN_LIMIT (D4h, Read/Write Word)
The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event 
that the input power rises above the value set in this register, the PIN over-power flags are set in the respective 
registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus read/
write word protocol. Reading and writing to this register should use the coefficients shown in Table 7-72.
Table 7-42. PIN_OP_WARN_LIMIT Register Description
Bit
Name
Description
Minimum Value
Maximum Value
Default Value
15:0
PIN_OP_WARN_LIMI
T
Input overpower 
warning threshold
0x0000h (0 W)
0x0FFFh (96.23xVCL/
RSNS W)
0x0FFFh (96.23xVCL/
RSNS W)
7.5.2.48 CLEAR_PIN_PEAK (D6h, Send Byte)
The CLEAR_PIN_PEAK command clears the READ_PIN_PEAK (A3h) register. This command uses the PMBus 
send byte protocol.
7.5.2.49 GATE_MASK (D7h, Read/Write Byte)
The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. 
When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers are 
still updated (STATUS, DIAGNOSTIC) and SMBA is still asserted. This register is accessed with the PMBus 
read/write byte protocol.
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CAUTION
Inhibiting the MOSFET switch off in response to overcurrent or circuit breaker fault conditions will 
likely result in the destruction of the MOSFET. This functionality must be used with great care and 
supervision.
Table 7-43. GATE_MASK Register Description
Bit
Description
Default
7
SCP FAULT
0
6
FET_FAIL
1
5
VIN UV FAULT
0
4
VIN OV FAULT
0
3
IIN/PFET FAULT
0
2
OVERTEMP FAULT
0
1
WATCH DOG FAULT
1
0
CIRCUIT BREAKER FAULT
0
The IIN/PFET fault refers to the input current fault and the MOSFET power dissipation fault. There is no input 
power fault detection, only input power warning detection.
7.5.2.50 ALERT_MASK (D8h, Read/Write Word)
The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each 
bit corresponds to one of the 16 different analog and digital faults or warnings that would normally result in 
an SMBA being asserted. When the corresponding bit is high, that condition does not cause the SMBA to 
be asserted. If that condition occurs, the registers where that condition is captured is still updated (STATUS 
registers, DIAGNOSTIC_WORD) and the external MOSFET gate control is still active (VIN_OV_FAULT, 
VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, SCP FAULT, OT_FAULT). This register is accessed with the 
PMBus read/write word protocol.
Table 7-44. ALERT_MASK Register Description
Bit
Description
Default
15
VOUT UNDERVOLTAGE WARN
1
14
IIN LIMIT WARN
1
13
VIN UNDERVOLTAGE WARN
1
12
VIN OVERVOLTAGE WARN
1
11
POWER GOOD
1
10
OVERTEMPERATURE WARN
1
9
WATCHDOG FAULT
0
8
OVERPOWER LIMIT WARN
1
7
SCP FAULT
0
6
FET_FAIL FAULT
0
5
VIN UNDERVOLTAGE FAULT
1
4
VIN OVERVOLTAGE FAULT
0
3
IIN/PFET FAULT
0
2
OVERTEMPERATURE FAULT
0
1
CML FAULT (communications fault)
0
0
CIRCUIT BREAKER FAULT
0
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7.5.2.51 READ_VAUX_AVG (D9h, Read Word)
The READ_VAUX_AVG command reports the 12-bit ADC measured average auxiliary voltage. If the data is not 
ready, the returned value is the previous averaged data. However, if there is no previously averaged data, the 
default value (0000h) is returned. Average count can be programmed through SAMPLES_FOR_AVG register. 
The contents of READ_VAUX_AVG register can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG 
register high. This data is read with the PMBus read word protocol. This register should use the coefficients 
shown in Table 7-72.
Table 7-45. READ_VAUX Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VAUX_AVG
Value measured for 
average auxiliary voltage 
source connected at the 
VAUX pin since reset or 
last clear
0x0000 (0V)
0x0FFF (2.97V)
7.5.2.52 BLOCK_READ (DAh, Block Read)
The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry 
information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the 
LM5066Hx in a single SMBus transaction. The block is 12-bytes long with telemetry information being sent out in 
the same manner as if an individual READ_XXX command had been issued (shown in Table 7-46). The contents 
of the block read register are updated every clock cycle as long as the SMBus interface is idle. BLOCK_READ 
also specifies that the VIN, VOUT, IIN and PIN measurements are all time-aligned. If separate commands 
are used, individual samples may not be time-aligned because of the delay necessary for the communication 
protocol.
The block read command is read through the PMBus block read protocol.
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Table 7-46. BLOCK_READ Register Format
Register
Size
Default
DIAGNOSTIC_WO
RD
1 word
0880h
READ_IIN
1 word
0000h
READ_VOUT
1 word
0000h
READ_VIN
1 word
0000h
READ_PIN
1 word
0000h
READ_TEMPERAT
URE_1
1 word
0000h
7.5.2.53 SAMPLES_FOR_AVG (DBh, Read/Write Byte)
The SAMPLES_FOR_AVG command is a manufacturer-specific command for setting the number of samples 
used in computing the average values for IIN, VIN, VOUT, and PIN and TEMPERATURE. The decimal 
equivalent of the AVGN nibble is the power of 2 samples, (for example, AVGN = 12 equates to N = 4096 
samples used in computing the average). The LM5066Hx supports average numbers of 1, 2, 4, 8, 16, 32, 64, 
128, 256, 512, 1024, 2048, and 4096. The SAMPLES_FOR_AVG number applies to average values of IIN, 
VIN, VOUT, and PIN simultaneously. The LM5066Hx uses simple averaging. This is accomplished by summing 
consecutive results up to the number programmed, then dividing by the number of samples. Averaging is 
calculated according to the following sequence:
Y = (X(N) + X(N-1) + ... + X(0)) / N
(5)
When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a 
whole new sequence begins that requires the same number of samples (in this example, 4096) to be taken 
before the new average is ready.
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Table 7-47. SAMPLES_FOR_AVG Register Description
AVGN (b)
N = 2AVGN
Averaging / Register Update Period (ms)
0000b
1
0.02
0001b
2
0.04
0010b
4
0.08
0011b
8
0.16
0100b
16
0.32
0101b
32
0.64
0110b
64
1.28
0111b
128
2.56
1000b
256
5.12
1001b
512
10.24
1010b
1024
20.48
1011b
2048
40.96
1100b
4096
81.92
Note that a change in the SAMPLES_FOR_AVG register is not reflected in the average telemetry measurements 
until the present averaging interval has completed. The default setting for AVGN is 1000b, or 08h.
The SAMPLES_FOR_AVG register is accessed with the PMBus read/write byte protocol.
Table 7-48. SAMPLES_FOR_AVG Register
VALUE
MEANING
DEFAULT
00h to 0Ch
Exponent (AVGN) for number of samples to average over
08h
7.5.2.54 READ_VIN_AVG (DCh, Read Word)
The READ_VIN_AVG command reports the 12-bit ADC measured input average voltage. If the data is not 
ready, the returned value is the previous averaged data. However, if there is no previously averaged data, the 
default value (0000h) is returned. Average count can be programmed through SAMPLES_FOR_AVG register. 
The contents of READ_VIN_AVG register can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG 
register high. This data is read with the PMBus read word protocol. This register should use the coefficients 
shown in Table 7-72.
Table 7-49. READ_VIN_AVG Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VIN_AVG
Value measured for 
average input voltage 
since reset or last clear
0x0000 (0V)
0x0FFF (89.1V)
7.5.2.55 READ_VOUT_AVG (DDh, Read Word)
The READ_VOUT_AVG command reports the 12-bit ADC measured current sense average voltage. The 
returned value is the default value (0000h) or previous data when the average data is not ready. Average 
count can be programmed through SAMPLES_FOR_AVG register. The contents of READ_VOUT_AVG register 
can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register high. This data is read with the 
PMBus read word protocol. This register should use the coefficients shown in Table 7-72.
Table 7-50. READ_VOUT_AVG Register Description
Bit
Name
Description
Minimum Value
Maximum Value
15:0
READ_VOUT_AVG
Value measured for 
average output voltage 
since reset or last clear
0x0000 (0V)
0x0FFF (89.1V)
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7.5.2.56 READ_IIN_AVG (DEh, Read Word)
The READ_IIN_AVG command reports the 12-bit ADC measured current sense average voltage. The returned 
value is the default value (0000h) or previous data when the average data is not ready. Average count can be 
programmed through SAMPLES_FOR_AVG register. The contents of READ_IIN_AVG register can be reset to 
zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register high. This data is read with the PMBus read word 
protocol. This register should use the coefficients shown in Table 7-72.
Table 7-51. READ_IIN_AVG Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_IIN_AVG
Value measured for 
average input current 
since reset or last clear
0x0000 (0A)
0x0FFF 
(1.08xVCL/RSNS 
A)
0x0000 (0A)
0x0FFF 
(2.16xVCL/RSNS 
A)
7.5.2.57 READ_PIN_AVG (DFh, Read Word)
The READ_AVG_PIN command reports the 12-bit ADC measured VIN x IIN product. The returned value 
is the default value (0000h) or previous data when the average data is not ready. Average count can be 
programmed through SAMPLES_FOR_AVG register. The contents of READ_PIN_AVG register can be reset to 
zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register high. This data is read with the PMBus read word 
protocol. This register should use the coefficients shown in Table 7-72.
Table 7-52. READ_PIN_AVG Register Description
Bit
Name
Description
ADC_CONFIG_2 [6] = 0
ADC_CONFIG_2 [6] = 1
Minimum Value
Maximum Value
Minimum Value
Maximum Value
15:0
READ_PIN_AV
G
Value measured 
for average input 
power since reset or 
last clear
0x0000 (0W)
0x0FFF 
(96.23xVCL/RSNS 
W)
0x0000 (0W)
0x0FFF 
(192.45xVCL/RSNS 
W)
7.5.2.58 CLEAR_BB_RAM (E0h, Send Byte)
The CLEAR_BB_RAM command is a manufacturer specific command that clears the blackbox RAM and 
restores its contents to default values. It is implemented using the PMBus Send Byte protocol and does not 
include a data byte. This command is write-only.
7.5.2.59 READ_DIAGNOSTIC_WORD (E1h, Read Word)
The READ_DIAGNOSTIC_WORD PMBus command reports all of the LM5066Hx faults and warnings in a 
single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read 
requests to various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD 
register. The READ_DIAGNOSTIC_WORD command should be read with the PMBus read word protocol. 
The READ_DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and 
AVG_BLOCK_READ operations. Note that if UVLO is pulled low to shutt OFF the FET, the diagnostic word 
will return 08E0h.
Table 7-53. DIAGNOSTIC_WORD Register Description
Bit
Description
Default
15
VOUT_UNDERVOLTAGE_WARN
0
14
IIN_OP_WARN
0
13
VIN_UNDERVOLTAGE_WARN
0
12
VIN_OVERVOLTAGE_WARN
0
11
POWER GOOD
1
10
OVER_TEMPERATURE_WARN
0
9
TIMER_LATCHED_OFF
0
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Table 7-53. DIAGNOSTIC_WORD Register Description (continued)
Bit
Description
Default
8
FET_FAIL
0
7
CONFIG_PRESET
1
6
DEVICE_OFF
0
5
VIN_UNDERVOLTAGE_FAULT
0
4
VIN_OVERVOLTAGE_FAULT
0
3
IIN_OC/PFET_OP_FAULT
0
2
OVER_TEMPERATURE_FAULT
0
1
CML_FAULT
0
0
CIRCUIT_BREAKER_FAULT
0
7.5.2.60 AVG_BLOCK_READ (E2h, Block Read)
The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average 
telemetry information (IIN, VOUT, VIN, and PIN) and temperature to capture all of the operating information 
of the part in a single PMBus transaction. The block is 12-bytes long with telemetry information sent out in 
the same manner as if an individual READ_XXX_AVG command had been issued (shown in Table 7-54). 
AVG_BLOCK_READ also specifies that the VIN, VOUT, IIN and TEMP measurements are all time-aligned 
whereas there is a chance they may not be if read with individual PMBus commands. To read data from the 
AVG_BLOCK_READ command, use the SMBus block read protocol.
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Table 7-54. AVG_BLOCK_READ Register Format
Register
Size
Default
DIAGNOSTIC_WO
RD
1 word
0880h
READ_IIN_AVG
1 word
0000h
READ_VOUT_AVG
1 word
0000h
READ_VIN_AVG
1 word
0000h
READ_PIN_AVG
1 word
0000h
READ_TEMP_AVG
1 word
0000h
7.5.2.61 BB_ERASE (E3h, Send Byte)
BB_ERASE is a manufacturer specific command which fills the EEPROM (where Blackbox information is stored) 
with all zeroes (0).
This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is 
write only.
7.5.2.62 BB_CONFIG (E4h, Read/Write Byte)
BB_CONFIG is a manufacturer-specific command for configuring or reading the behavior of the Blackbox 
function as described in Blackbox Fault Recording section.
This command uses the PMBus read or write byte protocol.
Table 7-55. BB_CONFIG Register Description
Bit
Name
Value
Description
Default
7
FET_OFF_WR
BB EEPROM write trigger
1
GATE1 turn OFF triggers 
write to BB EEPROM
0
0
GATE1 turn OFF does 
not triggers write to BB 
EEPROM
6
FLT_WR
BB EEPROM write trigger
1
PGD low triggers write to 
BB EEPROM
0
0
PGD low does not triggers 
write to BB EEPROM
5
ALERT_WR
BB EEPROM write trigger
1
SMBA assertion triggers 
write to BB EEPROM
0
0
SMBA assertion does 
not trigger write to BB 
EEPROM
4:2
Reserved
000
Reserved
000
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Table 7-55. BB_CONFIG Register Description (continued)
Bit
Name
Value
Description
Default
1:0
BB_TICK
Blackbox timestamp tick 
interval
11
3200µs
00
10
800µs
01
200µs
00
10µs
BB_CONFIG [5] needs to be used in conjunction with the ALERT_MASK register to determine which 
events trigger the Blackbox write to the external EEPROM.
7.5.2.63 OC_BLANKING_TIMERS (E5h, Read/Write Byte)
The OC_BLANKING_TIMERS register is a manufacturer-specific command used to configure or read the setup 
information for the Overcurrent Blanking Timers in the LM5066Hx device.
This command uses the PMBus read or write byte protocol.
Table 7-56. OC_BLANKING_TIMERS Register Description
Bit
Name
Value
Overcurrent Blanking 
Timer Duration (ms)
Default
7:4
Overcurrent Blanking2 
Timer
0xFh
95
0x7h
0xEh
9.5
0xDh
4.75
0xCh
3.8
0xBh
2.85
0xAh
1.9
0x9h
0.95
0x8h
0.76
0x7h
0.57
0x6h
0.38
0x5h
0.285
0x4h
0.19
0x3h
0.095
0x2h
0.057
0x1h
0.038
0x0h
0
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Table 7-56. OC_BLANKING_TIMERS Register Description (continued)
Bit
Name
Value
Overcurrent Blanking 
Timer Duration (ms)
Default
3:0
Overcurrent Blanking1 
Timer
0xFh
95
0x5h
0xEh
76
0xDh
57
0xCh
38
0xBh
19
0xAh
14.25
0x9h
9.5
0x8h
7.6
0x7h
3.8
0x6h
1.9
0x5h
0.95
0x4h
0.7125
0x3h
0.475
0x2h
0.095
0x1h
0.019
0x0h
0
7.5.2.64 DELAY_CONFIG (E7h, Read/Write Byte)
The DELAY_CONFIG register is a manufacturer-specific command used to configure the the delay time for 
digital insertion and digital retry configurations in the LM5066Hx device. This command uses the PMBus read or 
write byte protocol.
Table 7-57. The DELAY_CONFIG Register Description
Bit
Name
Value
Delay Time Duration
Default
7:4
Retry Delay Time
0xFh
95s
0x8h
0xEh
47.5s
0xDh
19s
0xCh
9.5s
0xBh
4.75s
0xAh
2.85s
0x9h
1.9s
0x8h
0.95s
0x7h
712.5ms
0x6h
475ms
0x5h
285ms
0x4h
190ms
0x3h
95ms
0x2h
47.5ms
0x1h
19ms
0x0h
9.5ms
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Table 7-57. The DELAY_CONFIG Register Description (continued)
Bit
Name
Value
Delay Time Duration
Default
3:0
Insertion Delay Time
0xFh
0.95s
0x4h
0xEh
665ms
0xDh
475ms
0xCh
285ms
0xBh
95ms
0xAh
85.5ms
0x9h
66.5ms
0x8h
47.5ms
0x7h
38ms
0x6h
28.5ms
0x5h
19ms
0x4h
9.5ms
0x3h
6.65ms
0x2h
4.75ms
0x1h
1.9ms
0x0h
0.95ms
7.5.2.65 WD_PLB_ TIMER (E8h, Read/Write Byte)
The WD_PLB_ TIMER register is a manufacturer-specific command used to configure the Watch dog timer and 
Maximum Power Limit Blanking Timer thresholds in the LM5066Hx device. This command uses the PMBus read 
or write byte protocol.
Table 7-58. The WD_PLB_ TIMER Register Description
Bit
Name
Value
Timer Duration (ms)
Factory Default
EEPROM Default
7:4
WatchDog Timer
0xFh
9500
0x6Fh
0xBFh
0xEh
4750
0xDh
2850
0xCh
1900
0xBh
950
0xAh
712.5
0x9h
475
0x8h
237.5
0x7h
190
0x6h
142.5
0x5h
95
0x4h
47.5
0x3h
38
0x2h
28.5
0x1h
19
0x0h
9.5
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Table 7-58. The WD_PLB_ TIMER Register Description (continued)
Bit
Name
Value
Timer Duration (ms)
Factory Default
EEPROM Default
3:0
Maximum Power Limit 
Blanking Timer
0xFh
95
0xFh
0xFh
0xEh
47.5
0xDh
19
0xCh
9.5
0xBh
4.75
0xAh
1.9
0x9h
0.95
0x8h
0.7125
0x7h
0.475
0x6h
0.38
0x5h
0.285
0x4h
0.19
0x3h
0.095
0x2h
0.057
0x1h
0.038
0x0h
0
7.5.2.66 PK_MIN_AVG (E9h, Read/Write Byte)
PK_MIN_AVG is a manufacturer-specific command that resets all the maximum, minimum, and 
average 
telemetry 
registers, 
such 
as 
READ_VIN_PEAK, 
READ_IIN_PEAK, 
READ_TEMP_PEAK, 
READ_PIN_PEAK, 
READ_VIN_MIN, 
READ_VOUT_MIN, 
READ_VIN_AVG, 
READ_VOUT_AVG, 
READ_IIN_AVG, READ_TEMP_AVG, and READ_PIN_AVG. This command uses the PMBus read or write byte 
protocol.
As soon as the PK_MIN_AVG command is executed to clear the peak, minimum, and average registers, the 
RESET_PEAK, READ_MIN, and READ_AVG bits are automatically cleared to zero (0).
Table 7-59. PK_MIN_AVG Register Description
Bit
Name
Value
Description
Default
7
RESET_PEAK
1
Reset all peak registers to 
0
0
0
No action
6
RESET_AVG
1
Reset all average registers 
to 0
0
0
No action
5
RESET_MIN
1
Reset all minimum 
registers to 0
0
0
No action
4:0
Reserved
0000
Reserved
0000
7.5.2.67 P2t TIMER (EAh, Read/Write Byte)
The P2t TIMER register is a command is used to configure the P2t regulation timer mode and maximum timer 
duration in the LM5066Hx device. This command uses the PMBus read or write byte protocol.
Table 7-60. P2t TIMER Register Description
Bit
Name
Value
Description
Default
7:5
Reserved
000
Reserved
000
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Table 7-60. P2t TIMER Register Description (continued)
Bit
Name
Value
Description
Default
4
P2t Timer Mode
1
Absolute Junction 
Temperature,
0
TJ,ABS = Tc + ∆TJ
0
Change in Junction 
temperature,
∆TJ Timer
3:0
P2t Timer Max Duration
0xFh
95ms
0xCh
0xEh
47.5ms
0xDh
19ms
0xCh
9.5ms
0xBh
6.65ms
0xAh
4.75ms
0x9h
1.9ms
0x8h
0.95ms
0x7h
855μs
0x6h
760μs
0x5h
665μs
0x4h
475μs
0x3h
380μs
0x2h
285μs
0x1h
190μs
0x0h
95μs
7.5.2.68 FETCH_BB_EEPROM (EBh, Send Byte)
FETCH_BB_EEPROM is a manufacturer specific command which loads the Blackbox contents from the internal 
EEPROM into the Blackbox shadow registers internal to the device. Those values can then be read back 
through PMBus using the READ_BB_EEPROM command.
This command uses the PMBus send byte protocol. This command is write only and has no data byte.
7.5.2.69 READ_BB_RAM (ECh, Block Read)
READ_BB_RAM is a manufacturer-specific command used to read the contents of the Blackbox buffer RAM, 
which is seven (7) bytes deep as described in Blackbox Fault Recording.
This command uses the PMBus block read protocol with a block size of seven (7).
Table 7-61 presents details of the Blackbox RAM registers. There are seven (7) Blackbox RAM registers, starting 
from BB_RAM_0 to BB_RAM_6. Descriptions of all seven (7) registers (BB_RAM_0 to BB_RAM_6) are identical.
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Table 7-61. BB_RAM Register Description
Bit
Name
Value
Description
Default
7:5
EVENT_ID
Event identifier
111
VIN_UV_WARN
000
110
VIN_OV_WARN
101
OC_WARN
100
OT_WARN
011
OC_DET
010
VIN_TRAN
001
IN_OP_WARN
000
None
4
BB_TMR_EXP
Blackbox timer expiry
1
Blackbox timer overflowed 
at least once since the last 
event
0
0
Blackbox timer has not 
overflowed
3:0
BB_TICK
0000
Blackbox tick timer
0000
The Blackbox RAM contents get reset under the following events:
•
Input power recycle at VIN or VDD pin
•
CLEAR_FAULTS command
•
OPERATION OFF command followed by OPERATION ON command
•
BB_CLEAR command
7.5.2.70 ADC_CONFIG_1 (EDh, Read/Write Byte)
ADC_CONFIG_1 is a manufacturer-specific command for configuring or reading channel selections and modes 
for ADC sampling. This command uses the PMBus read or write byte protocol.
The details of this register are shown in Table 7-62.
Table 7-62. ADC_CONFIG_1 Register Description
Bit
Name
Value
Description
Default
Access
7
EOC
End of conversion 
indication (Active 
Low)
Read
1
ADC is busy 
(Conversion in 
progress)
0
0
Conversion done
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Table 7-62. ADC_CONFIG_1 Register Description (continued)
Bit
Name
Value
Description
Default
Access
6
CONVST
Software conversion 
start control (used 
with MODE = 01)
Read/Write
1
Start conversion
0
0
Do not start 
conversion
5:4
MODE
ADC sampling mode
11
Continuous 
conversion - Single 
channel
00
10
01
Single channel single 
conversion – software 
controlled
00
Continuous 
conversion – auto 
sequenced
3:0
CONV_CH_SEL
Parameter/ADC 
Channel selection for 
sampling (MODE = 
01 or 10 or 11)
1010-1111
Reserved
0000
1001
ADDR2 (Applicable 
only in MODE = 01)
1000
GND (Applicable only 
in MODE = 01)
0111
VREF
0110
ADDR1 (Applicable 
only in MODE = 01)
0101
ADDR0 (Applicable 
only in MODE = 01)
0100
VAUX
0011
VTEMP
0010
IIN
0001
VOUT
0000
VIN
Note
MODE = 10 or 01 are debug only modes and not recommended to be used during normal operation 
as they prevent the ADC from sampling all the necessary signals needed for telemetry and protection.
7.5.2.71 ADC_CONFIG_2 (EEh, Read/Write Byte)
ADC_CONFIG_2 is a manufacturer-specific command for configuring or reading parameter selection and 
decimation rate (sample skip count) for high speed ADC sample buffering as described in READ_SAMPLE_BUF 
(C9h, Block Read).
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This command uses the PMBus read or write byte protocol.
The details of this register are shown in ADC_CONFIG_2 Register Description.
Table 7-63. ADC_CONFIG_2 Register Description
Bit
Name
Value
Description
Default
7
Reserved
0
Reserved
0
6
ADC Full Scale
1
ADC Full scale is 2xVCL
0
0
ADC Full scale is 1xVCL
5:3
BUF_CH_SEL
Parameter selection for 
buffering
111
Reserved (Will default to 
IIN)
000
110
101
100
VAUX
011
VTEMP
010
IIN
001
VOUT
000
VIN
2:0
DEC_RATE
Decimation rate (sample 
skip count) for ADC 
sample buffering
111
Decimation rate (sample 
skip count) = 7
0000
110
Decimation rate (sample 
skip count) = 6
101
Decimation rate (sample 
skip count) = 5
100
Decimation rate (sample 
skip count) = 4
011
Decimation rate (sample 
skip count) = 3
010
Decimation rate (sample 
skip count) = 2
001
Decimation rate (sample 
skip count) = 1
000
Decimation rate (sample 
skip count) = 0
7.5.2.72 DEVICE_SETUP1 (CCh, Read/Write Byte)
The DEVICE_SETUP1 command can be used to override pin settings to define operation of the LM5066Hx 
under host control. This command is accessed with the PMBus read/write byte protocol.
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Table 7-64. DEVICE_SETUP1 Register Description
Bit
Name
Value
Description
Default
7:5
Retry setting
111
Unlimited retries
000
110
Retry 16 times
101
Retry 8 times
100
Retry 4 times
011
Retry 2 times
010
Retry 1 times
001
No retries
000
Pin configured retries
4
Current limit setting
1
Low setting (25 mV)
0
0
High setting (50 mV)
3
CB/CL ratio
1
High setting (4x)
0
0
Low setting (2x)
2
Current limit configuration
1
Use SMBus settings
0
0
Use pin settings
1
Reserved
0
Reserved
0
0
Permanent Write Disable
1
Permanent Write Disable ON: Writing 02h to the 
WRITE_PROTECT (10h) register permanently 
disables writing to the device
0
0
Permanent Write Disable OFF: The permanent 
write disable function is not implemented, 
regardless of the value written to the 
WRITE_PROTECT (10h) register
To configure the current limit setting with register settings, it is necessary to set the current limit configuration 
bit (2) to 1 to enable the register to control the current limit function and the DEVICE_SETUP1 bit (4) and 
DEVICE_SETUP2 bits (3:5) to select the desired setting. If the current limit configuration bit is not set, the 
pin setting is used. The circuit breaker to current limit ratio value is set by the DEVICE_SETUP1 bit (3) and 
DEVICE_SETUP2 bit (6:7). Note that if the current limit configuration is changed, the samples for the telemetry 
averaging function are not reset. TI recommends to allow a full averaging update period with the new current 
limit configuration before processing the averaged data.
Note that the current limit configuration affects the coefficients used for the current and power measurements 
and warning registers.
7.5.2.73 DEVICE_SETUP2 (EFh, Read/Write Byte)
The DEVICE_SETUP2 command can be used to override pin settings to define operation of the LM5066Hx 
under host control. This command is accessed with the PMBus read/write byte protocol.
Table 7-65. DEVICE_SETUP2 Register Description
Bit
Name
Value
Description
Default
7:6
CB/CL Ratio2
11
3x
00
10
1.5x
01
1.2x
00
Setting as per bit (3) in DEVICE_SETUP1 
Register
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Table 7-65. DEVICE_SETUP2 Register Description (continued)
Bit
Name
Value
Description
Default
5:3
Current Limit Setting2
111
22.5mV
000
110
101
20mV
100
17.5mV
011
15mV
010
12.5mV
001
10mV
000
Setting as per bit (4) in DEVICE_SETUP1 
Register
2
Reserved
1
Fast Recovery after CB fault
1
Enabled
0
0
Disabled
0
VIN_TRAN_Enable
1
Input transient Blanking control Enable
0
0
Input transient Blanking control Disable
7.5.2.74 DEVICE_SETUP3 (F0h, Read/Write Byte)
The DEVICE_SETUP3 command can be used to configure the operation of the LM5066Hx under host control. 
This command is accessed with the PMBus read/write byte protocol.
Table 7-66. DEVICE_SETUP3 Register Description
Bit
Name
Value
Description
Default
7
Current Limiting Mode Disable
1
Disable current limiting after startup
0
0
Enable current limiting in all conditions
6
Power Limit Profile
1
Power limit Blanking
0
0
Constant Power Limit Profile
5:4
Foldback Current Limit
11
0.1x VCL
00
10
01
0.05x VCL
00
No Foldback during startup during startup
3:2
Overcurrent Blanking2 Threshold
11
2.25x VCL
00
10
2x VCL
01
1.75x VCL
00
1.5x VCL
1:0
Overcurrent Blanking1 Threshold
11
2x VCL
00
10
1.75x VCL
01
1.5x VCL
00
1.25x VCL
7.5.2.75 DEVICE_SETUP4 (CDh, Read/Write Byte)
The DEVICE_SETUP4 command can be used to configure the operation of the LM5066Hx under host control. 
This command is accessed with the PMBus read/write byte protocol.
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Table 7-67. DEVICE_SETUP4 Register Description
Bit
Name
Value
Description
Factory
Default
EEPROM Default
7
Immediate Retry 
after Circuit 
Breaker event
1
No Instant Retry after 30μs
0
1
0
Instant Retry after 30μs
6
Regulation Timer 
discharge current 
in CCT mode
1
75μA
0
0
0
2.5μA
5
SYNC Pin 
functionality
1
Enabled
0
0
0
Disabled
4
SFT_STRT Pin 
functionality
(LM5066H2)
1
Enabled
1
1
0
Disabled
3:2
Regulation Timer 
and Insertion, 
Retry Delay 
Setting
Regulation Timer 
Setting
Insertion and 
Retry Delay 
Setting
00
00
11
P2t timer
Digital insertion 
and digital retry 
timer
10
01
Constant current 
timer
Digital insertion 
and digital retry
timer
00
Constant current 
timer
Analog constant 
current timer
1:0
Power Limit 
Blanking VDS 
threshold
11
20V
01
01
10
15V
01
10V
00
5V
7.5.2.76 DEVICE_SETUP5 (CEh, Read/Write Byte)
The DEVICE_SETUP5 command can be used to configure the operation of the LM5066Hx under host control. 
This command is accessed with the PMBus read/write byte protocol.
Table 7-68. DEVICE_SETUP5 Register Description
Bit
Name
Value
Description
Default
7:5
Reserved
000
Reserved
000
4
GATE1 pull down for 
overcurrent fault after 
regulation timer expiry
1
1.5A
0
0
10mA
3
GATE2 pull down for 
overcurrent blanking 
after regulation timer 
expiry
or VDS > 2V
1
1.5A
0
0
10mA
2
GATE1 and GATE2 
pull down for 
over temperature, 
FET_FAIL, Operation 
OFF, Power Cycle, 
Watchdog expiry
1
1.5A
0
0
10mA
1
GATE1 and GATE2 
pull down for OVLO 
fault
1
1.5A
0
0
10mA
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Table 7-68. DEVICE_SETUP5 Register Description (continued)
Bit
Name
Value
Description
Default
0
GATE1 and GATE2 
pull down for UVLO 
fault
1
1.5A
0
0
10mA
7.5.2.77 IIN OFFSET CALIBRATION (F2h, Read/Write Byte)
IMON OFFSET CALIBRATION is a manufacturer-specific register that allows user to store offset factor for 
calibration of IIN readings captured by ADC. These calibration factor is applied for calculation of IIN , PIN and 
EIN parameters for reporting over PMBus. Reading this register should use the coefficients shown in Table 7-72. 
Accesses to this command should use the PMBus read or write byte protocol.
Table 7-69. IMON OFFSET CALIBRATION Register Description
Bit
Name
Value
Description
Default
Access
7
SIGN
Sign of the IIN offset 
correction factor
0
R/W
1
Negative Offset 
Factor
0
Positive Offset Factor
6:0
OFFSET_FACTOR
0 to 127
Offset factor added 
or subtracted from 
IIN ADC readings for 
correcting the offset 
error.
000
R/W
7.5.2.78 STATUS_MFR_SPECIFIC_2 (F3h, Read Word)
The STATUS_MFR_SPECIFIC_2 command is contains manufacturer specific status information. Accesses to 
this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should 
be removed and a CLEAR_FAULTS command should be issued. The STATUS_MFR_SPECIFIC_2 command 
should be read with the PMBus read word protocol.
Bit
Name
Value
Description
Default
15:13
Reserved
000
Reserved
000
12
WatchDog Fault
1
WatchDog Fault Occurred
0
0
WatchDog Fault has not 
occurred
11
SC_FLT
1
Short-circuit fault threshold 
crossed
0
0
Short-circuit fault threshold 
not crossed
10
RESERVED
0
RESERVED
0
9
EIN_OF_WARN
1
EIN register overflowed
0
0
EIN register not 
overflowed
8
VIN_TRAN
1
VIN transient detected
0
0
VIN transient not detected
7
Reserved
0
Reserved
0
6
EE_PROG
1
Internal EEPROM 
programmed
0
0
Internal EEPROM not 
programmed
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Bit
Name
Value
Description
Default
5
AVG_DONE
1
Average computation 
done
0
0
Average computation 
ongoing
4
Reserved
0
Reserved
0
3
RETRY_REC
1
Device has recovered 
from fault after auto-retry
0
0
Normal power up or 
Device has not recovered 
from fault after auto-retry
2
POWER_CYCLE_REC(co
ming from Analog to 
digital)
1
Device has successful 
startup after power cycle 
command
0
0
Normal power up or failed 
startup after power cycle 
command
1
INIT_DONE
1
Register initialization 
complete, All default 
configuration values 
loaded into operating 
memory
0
0
Register initialization not 
complete
0
Reserved
0
Reserved
0
EE_PROG bit will be cleared by OPERATION OFF/ON, CLEAR_FAULTS command.
7.5.2.79 READ_BB_EEPROM (F4h, Block Read)
READ_BB_EEPROM is a manufacturer-specific command used to read contents stored in the Blackbox shadow 
registers internal to the device. Before issuing this command, the FETCH_BB_EEPROM command needs 
to be sent to load the Blackbox contents from the internal EEPROM into the Blackbox shadow registers. 
READ_BB_EEPROM retrieves twenty-two (22) bytes of Blackbox information stored in the EEPROM as shown 
below.
•
BB_RAM_0 to BB_RAM_6 [Seven (7) bytes]
•
BB_TIMER [One (1) byte]
•
STATUS_WORD [Two (2) bytes]
•
STATUS_MFR_SPECIFIC [One (1) byte]
•
STATUS_MFR_SPECIFIC_2 [Two (2) byte]
•
STATUS_INPUT [One (1) byte]
•
VIN_PEAK [Two (2) bytes]
•
IIN_PEAK [Two (2) bytes]
•
PIN_PEAK [Two (2) bytes]
•
TEMPERATURE_PEAK [Two (2) bytes]
This command uses the PMBus® block read protocol with a block size of twenty-two (22)
7.5.2.80 BB_TIMER (F6h, Read Byte)
BB_TIMER is a manufacturer-specific command used to read the following:
•
Blackbox RAM address pointer, indicating which Blackbox RAM has been filled to date. After filling up all 
seven (7) Blackbox RAM locations, it resets to zero.
•
Blackbox timer expiry bit, showing if the Blackbox tick timer has overflowed at least once since the last event. 
This bit indicates if the Blackbox RAM event entries are relatively recent or old. This bit is latched when the 
timer overflows and resets to zero along with the free running timer when the next event occurs.
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•
Blackbox tick timer, a free running timer, which is reset to zero after every event. The timer update rate can 
be configured through the BB_CONFIG register. This allows users to tradeoff between fine resolution and 
longer time span depending on their debugging needs.
To access the BB_TIMER register, use the PMBus read byte protocol. The whole content of this register resets 
to zero (0) at the instant the CLEAR_FAULTS command is issued. The details of the BB_TIMER register are 
shown in BB_TIMER Register Description .
Table 7-70. BB_TIMER Register Description
Bit
Name
Value
Description
Default
Live/Latched
7:5
BB_PTR
BB RAM address 
pointer
000
Either all seven 
(7) Blackbox RAM 
registers are empty 
or all are filled up till 
date
000
Live
001
BB_RAM_0 filled up 
till date
010
BB_RAM_0 and 
BB_RAM_1 filled up 
till date
011
BB_RAM_0, 
BB_RAM_1, and 
BB_RAM_2 filled up 
till date
100
BB_RAM_0, 
BB_RAM_1, 
BB_RAM_2, and 
BB_RAM_3 filled up 
till date
101
BB_RAM_0, 
BB_RAM_1, 
BB_RAM_2, 
BB_RAM_3, and 
BB_RAM_4 filled up 
till date
110
BB_RAM_0, 
BB_RAM_1, 
BB_RAM_2, 
BB_RAM_3, 
BB_RAM_4, and 
BB_RAM_5 filled up 
till date
111
Reserved
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Table 7-70. BB_TIMER Register Description (continued)
Bit
Name
Value
Description
Default
Live/Latched
4
BB_TMR_EXP
Blackbox timer expiry
1
Blackbox timer 
overflowed at least 
once since the last 
event
0
Latched
0
Blackbox timer has 
not overflowed
3:0
BB_TICK
Blackbox timer
0000
Live
7.5.2.81 PMBUS_ADDR (F7h, Read/Write Byte)
PMBUS_ADDR is a manufacturer-specific command used for reading and configuring a user-specific device 
address apart from the addresses mentioned in Section 7.5.6. The device uses this address for I2C 
communication instead of the default value (0x40) when ADDR0, ADDR1 and ADDR2 pins are OPEN. This 
updated device address can be stored in the internal EEPROM and the device responds to this revised address 
upon power up next time.
This command uses the PMBus read or write byte protocol.
7.5.3 Reading and Writing Telemetry Data and Warning Thresholds
All measured telemetry data and user-programmed warning thresholds are communicated in 12-bit two’s 
complement binary numbers read or written in 2-byte increments conforming to the direct format as described 
in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II). The organization 
of the bits in the telemetry or warning word is shown in Table 7-71, where Bit_11 is the most significant bit 
(MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are 
constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value 
of the temperature word ranges from 0 to 65535.
Table 7-71. Telemetry and Warning Word Format
Byte
B7
B6
B5
B4
B3
B2
B1
B0
1
Bit_7
Bit_6
Bit_5
Bit_4
Bit_3
Bit_2
Bit_1
Bit_0
2
0
0
0
0
Bit_11
Bit_10
Bit_9
Bit_8
Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is 
accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System 
Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the 
values received into a reading of volts, amperes, watts, or other units using the following relationship:
(
)
R
1
x
Y
10
b
m
-
=
´
-
(6)
where
•
X = The calculated real-world value (volts, amps, watt, and so forth)
•
m = The slope coefficient
•
Y = A 2-byte two's complement integer received from device
•
b = The offset, a 2-byte two's complement integer
•
R = The exponent, a 1-byte two's complement integer
R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a 
register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.
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Table 7-72. Voltage, Current and Power Telemetry and Warning Conversion Coefficients (RSNS in mΩ)
Category
Register Name
ADC Full Scale 
Range
Current Limit 
Voltage (mV)
m
b
R
VAUX
READ_VAUX (D0h)
READ_VAUX_AVG (D9h)
NOT 
APPLICABLE
NOT 
APPLICABLE
13788
23
-1
VIN
READ_VIN (88h)
READ_VIN_MIN (A0h)
READ_VIN_PEAK (A1h)
VIN_UV_WARN_LIMIT (58h)
VIN_OV_WARN_LIMIT (57h)
4596
255
-2
READ_VIN_AVG (DCh)
4596
233
-2
VOUT
READ_VOUT (8Bh)
READ_VOUT_MIN (A4h)
VOUT_UV_WARN_LIMIT (43h)
4596
455
-2
READ_VOUT_AVG (DDh)
4596
417
-2
TEMP
READ_TEMPERATURE_1 (8Dh)
READ_TEMP_PEAK (C8h)
OT_FAULT_LIMIT (4Fh)
OT_WARN_LIMIT (51h)
100
26437
-2
READ_TEMP_AVG (C7h)
100
26437
-2
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Table 7-72. Voltage, Current and Power Telemetry and Warning Conversion Coefficients (RSNS in mΩ) 
(continued)
Category
Register Name
ADC Full Scale 
Range
Current Limit 
Voltage (mV)
m
b
R
IIN
READ_IIN (89h)
MFR_READ_IIN (D1h)
READ_IIN_PEAK (A2h)
IIN_OC_WARN_LIMIT (5Dh)
OC_WARN_LIMIT (F8h)
MFR_IIN_OC_WARN_LIMIT (D3h)
1xVCL
10
3791.7 x RSNS
10.25
-1
12.5
30333.3 x RSNS
395.57
-2
15
25277.8 x RSNS
-209
-2
17.5
21666.8 x RSNS
4.23
-2
20
18958.3 x RSNS
-246.36
-2
22.5
16851.9 x RSNS
-54.93
-2
25
15166.7 x RSNS
63.89
-2
50
7583.3 x RSNS
237.03
-2
2xVCL
10
18958.3 x RSNS
461.02
-2
12.5
15166.7 x RSNS
621.66
-2
15
12638.9 x RSNS
121.11
-2
17.5
10833.3 x RSNS
250.83
-2
20
9479.2 x RSNS
58.24
-2
22.5
8425.9 x RSNS
193.76
-2
25
7583.3 x RSNS
281.86
-2
50
3791.7 x RSNS
414.51
-2
READ_IIN_AVG (DEh)
1xVCL
10
3791.7 x RSNS
18.78
-1
12.5
30333.3 x RSNS
441.95
-2
15
25277.8 x RSNS
-150.06
-2
17.5
21666.7 x RSNS
27.64
-2
20
18958.3 x RSNS
-240.23
-2
22.5
16851.9 x RSNS
-51.31
-2
25
15166.7 x RSNS
58.36
-2
50
7583.3 x RSNS
220.65
-2
2xVCL
10
18958.3 x RSNS
457.6
-2
12.5
15166.7 x RSNS
614.42
-2
15
12638.9 x RSNS
103.87
-2
17.5
10833.3 x RSNS
259.76
-2
20
9479.2 x RSNS
53.34
-2
22.5
8425.9 x RSNS
178.01
-2
25
7583.3 x RSNS
333.99
-2
50
3791.7 x RSNS
401.74
-2
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Table 7-72. Voltage, Current and Power Telemetry and Warning Conversion Coefficients (RSNS in mΩ) 
(continued)
Category
Register Name
ADC Full Scale 
Range
Current Limit 
Voltage (mV)
m
b
R
IOUT
READ_IOUT (8Ch)
1xVCL
10
3791.7 x RSNS
18.78
-1
12.5
30333.3 x RSNS
441.95
-2
15
25277.8 x RSNS
-150.06
-2
17.5
21666.7 x RSNS
27.64
-2
20
18958.3 x RSNS
-240.23
-2
22.5
16851.9 x RSNS
-51.31
-2
25
15166.7 x RSNS
58.36
-2
50
7583.3 x RSNS
220.65
-2
2xVCL
10
18958.3 x RSNS
457.6
-2
12.5
15166.7 x RSNS
614.42
-2
15
12638.9 x RSNS
103.87
-2
17.5
10833.3 x RSNS
259.76
-2
20
9479.2 x RSNS
53.34
-2
22.5
8425.9 x RSNS
178.01
-2
25
7583.3 x RSNS
333.99
-2
50
3791.7 x RSNS
401.74
-2
POUT
READ_POUT (96h)
1xVCL
10
4255.5 x RSNS
6690
-3
12.5
3404.4 x RSNS
8003
-3
15
28370.1 x RSNS
4699
-4
17.5
24317.2 x RSNS
5764
-4
20
21277.6 x RSNS
4422
-4
22.5
18913.4 x RSNS
5378
-4
25
17022.1 x RSNS
6005
-4
50
8511.0 x RSNS
6868
-4
2xVCL
10
22979.8 x RSNS
6692
-4
12.5
18383.8 x RSNS
7998
-4
15
15319.9 x RSNS
4711
-4
17.5
13131.3 x RSNS
5779
-4
20
11489.9 x RSNS
4418
-4
22.5
10213.2 x RSNS
5387
-4
25
9191.9 x RSNS
6026
-4
50
4596 x RSNS
6871
-4
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Table 7-72. Voltage, Current and Power Telemetry and Warning Conversion Coefficients (RSNS in mΩ) 
(continued)
Category
Register Name
ADC Full Scale 
Range
Current Limit 
Voltage (mV)
m
b
R
PIN
READ_PIN (97h)
MFR_READ_PIN (D2h)
READ_PIN_PEAK (A3h)
MFR_PIN_OP_WARN_LIMIT (D4h)
1xVCL
10
4255.5 x RSNS
6690
-3
12.5
3404.4 x RSNS
8003
-3
15
28370.1 x RSNS
4699
-4
17.5
24317.2 x RSNS
5764
-4
20
21277.6 x RSNS
4422
-4
22.5
18913.4 x RSNS
5378
-4
25
17022.1 x RSNS
6005
-4
50
8511 x RSNS
6868
-4
2xVCL
10
22979.8 x RSNS
6692
-4
12.5
18383.8 x RSNS
7998
-4
15
15319.8 x RSNS
4711
-4
17.5
13131.3 x RSNS
5779
-4
20
11489.9 x RSNS
4418
-4
22.5
10213.2 x RSNS
5387
-4
25
9191.9 x RSNS
6026
-4
50
4596 x RSNS
6871
-4
READ_PIN_AVG (DFh)
1xVCL
10
4255.5 x RSNS
6829
-3
12.5
3404.4 x RSNS
8133
-3
15
28370.1 x RSNS
4788
-4
17.5
24317.2 x RSNS
5791
-4
20
21277.6 x RSNS
4418
-4
22.5
18913.4 x RSNS
5363
-4
25
17022.1 x RSNS
5942
-4
50
8511.0 x RSNS
6672
-4
2xVCL
10
22979.8 x RSNS
6834
-4
12.5
18383.8 x RSNS
8124
-4
15
15319.8 x RSNS
4799
-4
17.5
13131.3 x RSNS
5796
-4
20
11489.9 x RSNS
4410
-4
22.5
10213.2 x RSNS
5367
-4
25
9191.9 x RSNS
5934
-4
50
4596 x RSNS
6685
-4
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Table 7-72. Voltage, Current and Power Telemetry and Warning Conversion Coefficients (RSNS in mΩ) 
(continued)
Category
Register Name
ADC Full Scale 
Range
Current Limit 
Voltage (mV)
m
b
R
EIN
READ_EIN (86h)
1xVCL
10
16623.1 x RSNS
6675
-6
12.5
13298.5 x RSNS
8032
-6
15
11082.1x RSNS
4669
-6
17.5
9498.9 x RSNS
5784
-6
20
8311.6 x RSNS
4458
-6
22.5
7388.1 x RSNS
5356
-6
25
6649.2 x RSNS
6023
-6
50
3324.6 x RSNS
6898
-6
2xVCL
10
8976.5 x RSNS
6634
-6
12.5
7181.2 x RSNS
7945
-6
15
5984.3 x RSNS
4756
-6
17.5
5129.4 x RSNS
5767
-6
20
5129.4 x RSNS
4487
-6
22.5
3989.5 x RSNS
5361
-6
25
3590.6 x RSNS
6058
-6
50
17953 x RSNS
6843
-7
7.5.4 Determining Telemetry Coefficients Empirically With Linear Fit
The coefficients for telemetry measurements and warning thresholds presented in Table 7-72 are adequate for 
the majority of applications. Current and power coefficients are dependent on RSNS and must be calculated 
per application. These were obtained by characterizing multiple units over temperature and are considered 
optimal. The small signal nature of the current and power measurement makes it more susceptible to PCB 
parasitics than other telemetry channels. In addition there is some variation in RSNS and the LM5066Hx itself. 
This may cause slight variations in the optimum coefficients (m, b, and R) for converting from digital values 
to real world values (for example, amps and watts). To maximize telemetry accuracy, the coefficients can be 
calibrated for a given board using empirical methods. This would determine optimum coefficients to cancel out 
the error from PCB parasitics, RSNS variation, and the variation of LM5066Hx. It is not considered good practice 
to take measurements on one board and use the computed coefficients for all units in production, because the 
RSNS and the LM5066Hx on a given board are randomly chosen and do not represent a statistical mean. It is 
recommended to either calibrate all boards individually or to use the recommended coefficients from Table 7-72 .
The optimal current coefficients for a specific board can be determined using the following method:
1.
While the LM5066Hx is in normal operation, measure the voltage across the sense resistor using Kelvin test 
points and a high accuracy DVM while controlling the load current. Record the integer value returned by the 
READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more 
voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should 
span nearly the full-scale range of the current (for example, voltage across RSNS of 5 and 20 mV).
2.
Convert the measured voltages to currents by dividing them by the value of RSNS. For best accuracy, the 
value of RSNS should be measured. Table 7-73 assumes a sense resistor value of 5 mΩ.
Table 7-73. Measurements for Linear Fit Determination of Current Coefficients
Measured Voltage Across
RSNS (V)
Measured Current
(A)
READ_AVG_IIN
(Integer Value)
0.005
1
568
0.01
2
1108
0.02
4
2185
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3.
Using the spreadsheet (or a math program) determine the slope and the y-intercept of the data returned by 
the READ_AVG_IIN command versus the measured current. For the data shown in Table 7-72:
•
READ_AVG_IN value = slope × (Measured Current) + (y-intercept)
•
Slope = 538.9
•
Y-intercept = 29.5
4.
To determine the m coefficient, simply shift the decimal point of the calculated slope to arrive at integer with 
a suitable number of significant digits for accuracy (typically 4) while staying with the range of –32768 to 
32767. This shift in the decimal point equates to the R coefficient. For the slope value shown in the previous 
step, the decimal point would be shifted to the right once hence R = –1.
5.
After the R coefficient has been determined, the b coefficient is found by multiplying the y-intercept by  10 –R. 
In this case the value of b = 295.
•
Calculated current coefficients:
•
m = 5389
•
b = 295
•
R = –1
(
)
R
1
x
Y
10
b
m
-
=
´
-
(7)
where
•
X = The calculated real-world value (volts, amps, watts, temperature)
•
m = The slope coefficient, is the 2-byte, two's complement integer
•
Y = A 2-byte two's complement integer received from device
•
b = The offset, a 2-byte two's complement integer
•
R = The exponent, a 1-byte two's complement integer
This procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting 
measured current for some other parameter (for example, power or voltage).
7.5.5 Writing Telemetry Data
There are several locations that require writing data if their optional usage is desired. Use the same coefficients 
previously calculated for your application, and apply them using this method as prescribed by the PMBus 
revision section 7.2.2 Sending a Value
(
)
R
Y
mX
b
10
=
+
´
(8)
where
•
X = The calculated real-world value (volts, amps, watts, temperature)
•
m = The slope coefficient is the 2-byte, two's complement integer
•
Y = A 2-byte two's complement integer received from device
•
b = The offset, a 2-byte two's complement integer
•
R = The exponent, a 1-byte two's complement integer
7.5.6 PMBus Address Lines (ADR0, ADR1, ADR2)
The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 
27 addresses for communicating with the LM5066Hx. Table 7-74 depicts 7-bit addresses (eighth bit is read/write 
bit).
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Table 7-74. Device Addressing
ADR2
ADR1
ADR0
DECODED ADDRESS
Z
Z
Z
40h (Default)
Can be overwritten 
with a user defined 
address programmed into 
PMBUS_ADDR register
Z
Z
0
41h
Z
Z
1
42h
Z
0
Z
43h
Z
0
0
44h
Z
0
1
45h
Z
1
Z
46h
Z
1
0
47h
Z
1
1
10h
0
Z
Z
11h
0
Z
0
12h
0
Z
1
13h
0
0
Z
14h
0
0
0
15h
0
0
1
16h
0
1
Z
17h
0
1
0
50h
0
1
1
51h
1
Z
Z
52h
1
Z
0
53h
1
Z
1
54h
1
0
Z
55h
1
0
0
56h
1
0
1
57h
1
1
Z
58h
1
1
0
59h
1
1
1
5Ah
7.5.7 SMBA Response
The SMBA effectively has two masks:
•
The alert mask register at D8h
•
The ARA automatic mask.
The ARA automatic mask is a mask that is set in response to a successful ARA read. An ARA read operation 
returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful 
ARA read means that this part was the one that returned its address. When a part responds to the ARA read, 
it releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its 
address, the SMBA signal de-asserts.
The way that the LM5066Hx releases the SMBA signal is by setting the ARA automatic mask bit for all fault 
conditions present at the time of the ARA read. All status registers will still the fault condition, but it does 
not generate a SMBA on that fault again until the ARA automatic mask is cleared by the host issuing a 
CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on 
a part, even if the ARA read is not done. Figure 7-9 depicts a schematic version of this flow.
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Alert Mask D8h
From PMBus
From other 
fault inputs
ARA Auto Mask
Set
Clear
Fault Condition
ARA Operation Flag Succeeded
Clear_Fault Command Received
SMBA
Figure 7-9. Typical Flow Schematic for SMBA Fault
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, 
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for 
determining suitability of components for their purposes, as well as validating and testing their design 
implementation to confirm system functionality.
8.1 Application Information
The LM5066Hx is a hot swap with a PMBus interface that provides current, voltage, power, and status 
information to the host. As a hot swap controller, it is used to manage inrush current and protect in the event of 
faults.
When designing a hotswap, three key scenarios should be considered:
•
Start-up
•
The output of a hot swap controller is shorted to ground when the hot swap controller is on. This is often 
referred to as an output hot-short.
•
Powering up a board when the output and ground are shorted. This is usually called a start-into-short.
All of these scenarios place a lot of stress on the hotswap MOSFET, and take special care when designing the 
hotswap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the following 
sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends 
using the LM5066Hx Design Calculator.
8.2 Typical Application
8.2.1 54V, 100A PMBus Hot Swap Design
This section describes the design procedure for a 54V, 100A PMBUS hot swap design using the LM5066H1 
controller.
OUT
UVLO/EN
VIN
GATE
DIODE
R3
FB
OVLO
SDAI
SCL
PGD
SENSE
VDD
SMBus
Interface
SMBA
CL
RETRY
VAUX
VDD
VREF
TIMER
PWR
AGND
LM5066H1
VOUT
COUT
VIN
1
F
1
F
RPWR
ADR2
ADR1
ADR0
VDD
VIN_K
GND
SDAO
RSNS
R4
R1
CTIMER
R5
R6
CIN
D1
D2
QT
Q1
R2
IMON
RIMON
Cdvdt
Figure 8-1. Typical Application Circuit
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8.2.1.1 Design Requirements
Table 8-1 summarizes the design parameters that must be known before designing a hotswap circuit. When 
charging the output capacitor through the hotswap MOSFET, the FET’s total energy dissipation equals the total 
energy stored in the output capacitor (1/2 CV2). Thus, both the input voltage and output capacitance determine 
the stress experienced by the MOSFET during start-up. The maximum load current drives the current limit and 
sense resistor selection. Additionally, the maximum load current, maximum ambient temperature, and thermal 
properties of the PCB (RθCA) influence the selection of the MOSFET, including the RDSON and he number of 
MOSFETs used. RθCA is a strong function of the layout and the amount of copper that is connected to the drain 
of the MOSFET. Note that the drain is not electrically connected to the ground plane; therefore, the ground plane 
cannot be used to aid in heat dissipation. This design example uses RθCA = 25°C/W, which is similar to the 
LM5066H1 and LM5066H2 evaluation modules. It is a good practice to measure the RθCA of a given design after 
the physical PCBs are available.
Finally, it is important to understand what test conditions the hotswap needs to pass. In general, a hotswap is 
designed to pass both a hot-short and a start into a short, which are described in the previous section. Also, 
TI recommends keeping the load OFF until the hotswap is fully powered up. Starting the load early causes 
unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start up.
Table 8-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
40 to 60V
Maximum load current
100A
Maximum output capacitance of the hotswap
5mF
Maximum ambient temperature
55°C
MOSFET RθCA (function of layout)
25°C/W
Pass hot-short on output?
Yes
Pass a start into short?
Yes
Is the load off until PG asserts?
Yes
Can a hot board be plugged back in?
Yes
8.2.1.2 Detailed Design-In Procedure
8.2.1.2.1 Selecting the Hotswap FETs
It is critical to select the correct MOSFET for a hotswap design. The device must meet the following 
requirements:
•
The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by 
transients. For most 54V systems, a 100V FET is a good choice.
•
The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, and start into short.
•
RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of 
the FET. In fact, TI recommends keeping the steady-state FET temperature below 125°C to allow margin to 
handle transients.
•
The maximum continuous current rating should be above the maximum load current, and the pulsed-drain 
current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first 
three requirements also pass these two.
•
A VGS rating of ±20 V is required because the LM5066Hx can pull up the gate as high as 16V above source.
For this design, the PSMN2R3-100SSE was selected for its low RDSON and superior SOA. Four (4) MOSFETs 
are used in parallel in this design example. After selecting the MOSFET, the maximum steady-state case 
temperature can be computed as follows:
2
C,MAX
A,MAX
CA
LOAD,MAX
DSON
J
T
T
R
I
R
(T )
q
=
+
´
´
(9)
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Note that the RDSON is a strong function of junction temperature, which for most LFPAK88 MOSFETs is very 
close to the case temperature. A few iterations of the previous equations may be necessary to converge on the 
final RDSON and TC,MAX value. According to the PSMN2R3-100SSE data sheet, its RDSON becomes 1.75 times at 
120°C. Equation 10 uses this RDSON value to compute the TC,MAX. Note that the computed TC,MAX is close to the 
junction temperature assumed for RDSON. Thus, no further iterations are necessary.
TC, MAX = 55°C + 25°C
W ×
100A
4
2 × 1.75 × 2.3mΩ = 118°C
(10)
8.2.1.2.2 dv/dt based Start-Up
For designs with large load currents and output capacitances, using a power-limit-based start-up can be 
impractical. Fundamentally, increasing load currents reduces the sense resistor, which increases the minimum 
power limit. Using a larger output capacitor results in a longer start-up time and requires a longer timer. Thus, 
a longer timer and a larger power limit setting are required, which places more stress on the MOSFET during a 
hot-short or a start into short. Eventually, there will be no FETs that can support such a requirement.
To avoid this problem, a dv/dt limiting capacitor (Cdv/dt) can be used to limit the slew rate of the gate and the 
output voltage. The inrush current can be set arbitrarily small by reducing the slew rate of VOUT. In addition, 
the power limit is set to satisfy the minimum power limit requirement and to keep the timer from running during 
start-up (make PLIM / VINMAX > IINR). Because the timer does not run during start-up, it can be made arbitrarily 
small to reduce the stress that the MOSFET experiences during a start into a short or a hot-short.
8.2.1.2.2.1 Choosing the VOUT Slew Rate
The inrush current should be kept low enough to keep the MOSFET within its SOA during start-up. Note that the 
total energy dissipated in the MOSFET during start-up is constant regardless of the inrush time. Thus, stretching 
it out over a longer time always reduces the stress on the MOSFET as long as the load is off during start-up.
When choosing a target slew rate, one should pick a reasonable number, check the SOA, and reduce the slew 
rate if necessary. Using 0.3V/ms as a starting point, the inrush current can be computed as follows:
IINR = COUT ×
dVOUT
dt
= 5mF × 0.3V
ms = 1.5A
(11)
Assuming a maximum input voltage of 60V, it takes around 200ms to start up. Note that the power dissipation 
of the FET starts at VIN,MAX × IINR and reduces to 0 as the VDS of the MOSFET is reduced. Note that the 
SOA curves assume the same power dissipation for a given time. A conservative approach is to assume an 
equivalent power profile where PFET = VIN,MAX × IINR for t = tstart-up / 2. In this instance, the SOA can be checked 
by looking at a 60V, 1.5A, 100ms pulse. Using the SOA plot from the PSMN2R3-100SSE MOSFET datasheet, 
the MOSFET can handle 60V, 6A for 100ms at an ambient temperature of 25°C. This value has to also be 
derated for temperature. For this calculation, it is assumed that TC can equal TC,MAX when the board is plugged 
in. This would only occur if a hot board is unplugged, then plugged back in before it cools off. This is worst case 
and for many applications, the TA,MAX can be used for this derating.
ISOA 100ms,  TC, MAX = ISOA 100ms,  25°C ×
TJ, ABSMAX −TC, MAX
TJ, ABSMAX −25°C
= 6A × 175°C −118°C
175°C −25°C = 2.3A
(12)
This calculation shows that the MOSFET stays well within its SOA during a start-up if the slew rate is 0.3V/ms. 
Note that if the load is off during start-up, the total energy dissipated in the FET is constant regardless of the 
slew rate. Thus, a lower slew rate always places less stress on the FET. To ensure that the slew rate is at most 
0.3V/ms, the Cdv/dt should be chosen as follows:
Cdv/dt =
IGATE, SOURCE
0.3V/ms
=
21µA
0.3V/ms = 70nF
(13)
The closest value of 68nF is selected. Next, the typical slew rate and start time can be computed to be 0.31V/ms 
as shown in Equation 14, making the typical start time around 200ms.
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ΔVOUT
Δt
=
IGATE, SOURCE
Cdv/dt
= 21µA
68nF = 0.31V/ms
(14)
8.2.1.2.3 Select RSNS and CL Setting
LM5066H1 can be used with a VCL of 25 or 50mV using CL pin configurations (Connect CL pin to GND to set 
the nominal overcurrent threshold at 50mV. Connecting CL to VDD sets the overcurrent threshold to be 25mV). 
Using the DEVICE_SETUP2 (EFh, Read/Write Word) register, the current limit can be set at 10mV, 12.5mV, 
15mV, 17.5mV, 20mV, and 22.5mV. TI recommends targeting a current limit that is at least 10% above the 
maximum load current to account for the tolerance of the LM5066H1 current limit. Targeting a current limit of 
110A, the sense resistor can be computed as follows:
RSNS, CLC =
VCL
ILIM = 25mV
110A = 227µΩ
(15)
Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense 
resistor along with a resistor divider can be used as shown in Figure 8-2.
RSNS
R1
R2
VIN_K
SENSE
Figure 8-2. SENSE Resistor Divider
The next larger available sense resistor should be chosen (250µΩ in this case). The ratio of R1 and R2 can be 
computed as follows:
R1
R2 =
RSNS, CLC
RSNS −RSNS, CLC =
227
250 −227 = 9.9
(16)
Note that the SENSE pin pulls 25μA of current, which creates an offset across R2. TI recommends keeping R2 
below 10Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring 
error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance 
(RSNS,EFF) using Equation 17 and use that in all equations instead of RSNS.
SNS
1
SNS,EFF
1
2
R
R
R
R
R
´
=
+
(17)
R1 is selected as 10Ω, R2 becomes 1.01Ω. Closest selected value of R2 is 1Ω.
Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the 
next smaller available sense resistor.
8.2.1.2.4 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the 
LM5066H1 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage 
across the sense resistor (VSNS) to a very-low value. VSNS can be computed as shown in Equation 18.
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LIM
SNS
SNS
DS
P
R
V
V
´
=
(18)
To avoid significant degradation of the power limiting, TI does not recommend a VSNS of less than 0.5mV. Based 
on this requirement, the minimum allowed power limit can be computed as follows:
PLIM, MIN =
VSNS, MIN × VIN, MAX
RSNS
= 1mV × 60V
0.227mΩ
= 264W
(19)
In most applications, the power limit can be set to PLIM,MIN, using Equation 20. 270W of power limit is considered 
here.
PLIM W =
RPWR kΩ × 6
RSNS mΩ
(20)
The closest available resistor should be selected. In this case, a 10kΩ resistor was chosen.
8.2.1.2.5 Set Fault Timer
The fault timer runs when the hotswap is in power limit or current limit. Based on the PSMN2R3-100SSE 
MOSFET SOA plot, a 1ms fault timer duration is considered, which provides enough MOSFET SOA margin. 
CTIMER can be computed as follows:
CTIMER =
tflt × itimer
Vtimer
= 1ms × 75µA
3.9V
= 20nF
(21)
The fault timer capacitor is selected as 20nF.
8.2.1.2.6 Check MOSFET SOA
When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all 
test conditions. During a hot-short, the circuit breaker trips and the LM5066H1 restarts into power limit until the 
timer runs out. In the worst case, the MOSFET’s VDS equals VIN, MAX, IDS equals PLIM / VIN, MAX, and the stress 
event lasts for tflt. For this design example, the MOSFET has 60V, 4.5A across it for 1ms.
Based on the SOA of the PSMN2R3-100SSE, it can handle 60V, 30A for 1ms at an ambient temperature of 
25°C.
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be 
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX, using Equation 22:
ISOA 1ms,  TC, MAX = ISOA 1ms,  25°C ×
TJ, ABSMAX −TC, MAX
TJ, ABSMAX −25°C
= 30A × 175°C −118°C
175°C −25°C = 11.4A
(22)
Based on this calculation, the MOSFET can handle 11.4A, 60V for 1ms at an elevated case temperature of 
118°C, but is only required to handle 4.5A during a hot-short. Thus, there is a good margin, and the design is 
robust. In general, TI recommends that the MOSFET can handle 1.3 times more than what is required during a 
hot-short. This provides margin to account for the variance of the power limit and fault time.
8.2.1.2.7 Set UVLO and OVLO Thresholds
By programming the UVLO and OVLO thresholds, the LM5066Hx enables the series-pass device (Q1) when the 
input supply voltage (VIN) is within the desired operational range. If VIN is below the UVLO threshold or above 
the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
8.2.1.2.7.1 Option A
The configuration shown in Figure 8-3 requires three resistors (R1 to R3) to set the thresholds.
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VIN
UVLO/EN
OVLO
GND
R1
R2
R3
2.48 V
2.46 V
TIMER AND 
GATE
LOGIC CONTROL
VIN
21 PA
20 PA
Figure 8-3. UVLO And OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
•
Choose the upper UVLO threshold (VUVH) and the lower UVLO threshold (VUVL).
•
Choose the upper OVLO threshold (VOVH).
•
The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the 
values for R1 to R3 are determined. If VOVL must be accurately defined in addition to the other three 
thresholds, see Option B. The resistors are calculated as follows:
UV(HYS)
UVH
UVL
V
V
V
R1
20 A
20 A
-
=
=
m
m
(23)
(
)
UVL
OVH
UVL
R1 V
2.46V
R3
V
V
2.48V
´
´
=
´
-
(24)
UVL
2.48V
R1
R2
R3
V
2.48V
´
=
-
-
(25)
The lower OVLO threshold is calculated from:
(
)
OVL
2.46V
V
R1 R2
21 A
2.46V
R3
é
ù
æ
ö
æ
ö
=
+
´
-
m
+
ê
ú
ç
÷
ç
÷
è
ø
ê
ú
è
ø
ë
û
(26)
When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the 
following:
UVH
2.48V
V
 2.48V
R1
20
A
R2
R3
æ
ö
=
+
´
+
m
ç
÷
+
è
ø
(27)
(
)
UVL
2.48V
R1 R2
R3
V
R2
R3
´
+
+
=
+
(28)
UV(HYS)
V
R1 20
A
=
´
m
(29)
(
)
OVH
2.46V
R1 R2
R3
V
R3
´
+
+
=
(30)
(
)
OVL
2.46V
V
21 A
R1 R2
2.46V
R3
æ
ö
=
-
m
´
+
+
ç
÷
è
ø
(31)
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(
)
OV(HYS)
V
 R1 R2
21 A
=
+
´
m
(32)
8.2.1.2.7.2 Option B
If all four thresholds must be accurately defined, the configuration in Figure 8-4 can be used.
VIN
UVLO/EN
OVLO
GND
R1
R3
R4
2.48 V
2.46 V
TIMER AND 
GATE
LOGIC CONTROL
VIN
R2
21 PA
20 PA
Figure 8-4. Programming the Four Thresholds
The four resistor values are calculated as follows:
•
Choose the upper and lower UVLO thresholds (VUVH) and (VUVL).
UV(HYS)
UVH
UVL
V
V
V
R1
20
A
20
A
-
=
=
m
m
(33)
UVL
2.48V
R1
R2
 V
2.48V
´
=
-
(34)
•
Choose the upper and lower OVLO threshold (VOVH) and (VOVL).
OVH
OVL
V
V
R3
21 A
-
=
m
(35)
(
)
OVH
2.46V
R3
R4
V
2.46V
´
=
-
(36)
•
When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the 
following:
UVH
2.48V
V
2.48V
R1
20
A
R2
é
ù
æ
ö
=
+
´
+
m
ê
ú
ç
÷
è
ø
ë
û
(37)
(
)
UVL
2.48V
R1 R2
V
R2
´
+
=
(38)
UV(HYS)
V
R1 20
A
=
´
m
(39)
(
)
OVH
2.46V
R3
R4
V
R4
´
+
=
(40)
OVL
2.46V
V
2.46V
R3
21 A
R4
é
ù
æ
ö
=
+
´
-
m
ê
ú
ç
÷
è
ø
ë
û
(41)
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8.2.1.2.7.3 Option C
The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 8-5. Q1 is 
switched on when the VIN voltage reaches the POREN threshold (≊8.6 V). The OVLO thresholds are set using 
R3, R4. Their values are calculated using the procedure in Option B.
VIN
UVLO/EN
OVLO
GND
10 k
R3
R4
2.48 V
2.46 V
TIMER AND 
GATE
LOGIC CONTROL
VIN
21 PA
20 PA
Figure 8-5. UVLO = POREN 
8.2.1.2.7.4 Option D
The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in 
Option B or Option C.
For this design example, option B was used and the following options were targeted: VUVH = 38 V, VUVL = 35 
V, VOVH = 65 V, and VOVL = 63 V. The VUVH and VOVL were chosen to be 5% below or above the input voltage 
range of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed 
using the following equations:
(
)
(
)
(
)
(
)
UVH
UVL
UVL
OVH
OVL
OVH
V
V
38 V
35 V
R1
150k
20µA
20µA
2.48 V
R1
2.48 V
150k
R2
11.44k
V
2.48 V
35V
2.48 V
V
V
65 V
63 V
R3
95.24k
21µA
21µA
2.46 V
R3
2.46 V
95.24k
R4
3.75k
V
2.46 V
65V
2.46 V
-
-
=
=
=
W
´
´
W
=
=
=
W
-
-
-
-
=
=
=
W
´
´
W
=
=
=
W
-
-
(42)
Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74 
kΩ.
8.2.1.2.8 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of 
sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an 
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be 
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds 
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to 
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored 
as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block 
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As 
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out 
of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either 
the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be 
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
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When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is 
disabled allowing PGD to rise to VPGD through the pullup resistor, RPG, as shown in Figure 8-7. The pullup 
voltage (VPGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD 
is a convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on PGD during 
power-up. If a delay is required at PGD, suggested circuits are shown in Figure 8-8. In Figure 8-8(A), capacitor 
CPG adds delay to the rising edge, but not to the falling edge. In Figure 8-8(B), the rising edge is delayed by 
RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode 
across RPG2 (Figure 8-8(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a 
long delay at the falling edge.
OUT
FB
GND
PGD
GATE
UV
OV
Q1
VOUT
R5
R6
2.46 V
20 PA
Figure 8-6. Programming the PGD Threshold
GND
RPG
Power Good
VPGD
PGD
Figure 8-7. Power Good Output
GND
RPG1
VPGD
CPG
PGD
GND
RPG1
Power 
Good
VPGD
CPG
PGD
RPG2
GND
RPG1
VPGD
CPG
PGD
RPG2
C) Short Delay at Rising Edge and
     Long Delay at Falling Edge or
     Equal Delays
B)  Long Delay at Rising Edge,
     Short Delay at Falling Edge
A)  Delay at Rising Edge Only
Power 
Good
Power
Good
Figure 8-8. Adding Delay to the Power Good Output Pin
TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted 
under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are 
computed using the following equations:
PGDH
PGDL
V
V
38 V
35 V
R5
150k
20µA
20µA
-
-
=
=
=
W
(43)
(
)
(
)
PGDH
2.46 V
R5
2.46 V
150k
R6
10.38k
V
2.46 V
38V
2.46 V
´
´
W
=
=
=
W
-
-
(44)
Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.
8.2.1.2.9 Input and Output Protection
Proper operation of the LM5066Hx hot swap circuit requires a voltage clamping element present on the supply 
side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in Figure 8-9. 
The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load 
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current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the 
FET shutts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage 
to under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice.
If the load powered by the LM5066Hx hot swap circuit has inductive characteristics, a Schottky diode is required 
across the LM5066Hx’s output, along with some load capacitance. The capacitance and the diode are necessary 
to limit the negative excursion at the OUT pin when the load current is shut off.
LM5066H1
Inductive
Load
VIN
GND
+48 V
GND
LIVE
POWER 
SOURCE
PLUG-IN BOARD
OUT
Q1
SENSE
VIN_K
AGND
VOUT
RSNS
VIN
CL
Z1
D1
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Figure 8-9. Output Diode Required for Inductive Loads
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8.2.1.3 Application Curves
IIN
Figure 8-10. Insertion Delay
VIN = 54V
Figure 8-11. Start-Up
Figure 8-12. Start-Up Into Short-circuit
Figure 8-13. Start-Up Into Short-circuit
Figure 8-14. Undervoltage Lockout
Figure 8-15. Overvoltage Lockout
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Figure 8-16. Load Transient
Figure 8-17. Load Transient Followed by 
Overcurrent Event
Figure 8-18. Overcurrent Event (zoomed)
Figure 8-19. Hotshort on Output (zoomed out)
Figure 8-20. Hotshort on Output (zoomed in)
8.3 Power Supply Recommendations
In general, the LM5066Hx behavior is more reliable if it is supplied from a very regulated power supply. However, 
high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is 
expected in the end system, TI recommends to place a 1µF ceramic capacitor to ground close to the source of 
the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be 
necessary to avoid nuisance trips.
8.4 Layout
8.4.1 Layout Guidelines
The following guidelines should be followed when designing the PC board for the LM5066Hx:
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1.
Place the LM5066Hx close to the board’s input connector to minimize trace inductance from the connector to 
the MOSFET.
2.
Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066Hx to help minimize voltage 
transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN 
is just lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage 
can easily occur when the load current is shut off. TI recommends to test the VIN input voltage transient 
performance of the circuit by current limiting or shorting the load and measuring the peak input voltage 
transient.
3.
Place a 1µF ceramic capacitor as close as possible to VREF pin.
4.
Place a 1µF ceramic capacitor as close as possible to VDD pin.
5.
The sense resistor (RSNS) should be placed close to the LM5066Hx. A trace should connect the VIN pad 
and Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin 
techniques as shown in Figure 8-22.
6.
The high current path from the board’s input to the load (through Q1), and the return path, should be parallel 
and close to each other to minimize loop inductance.
7.
The AGND and GND connections should be connected at the pins of the device. The ground connections 
for the various components around the LM5066Hx should be connected directly to each other, and to the 
LM5066Hx’s GND and AGND pin connection, and then connected to the system ground at one point. Do not 
connect the various component grounds to each other through the high current ground line.
8.
Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and 
turn-off.
9.
The board’s edge connector can be designed such that the LM5066Hx detects through the UVLO/EN 
pin that the board is being removed, and responds by turning off the load before the supply voltage is 
disconnected. For example, in , the voltage at the UVLO/EN pin goes to ground before VIN is removed from 
the LM5066Hx as a result of the shorter edge connector pin. When the board is inserted into the edge 
connector, the system voltage is applied to the LM5066Hx’s VIN pin before the UVLO voltage is taken high, 
thereby allowing the LM5066Hx to turn on the output in a controlled fashion.
8.4.2 Layout Example
Q1
Z1/C1
R2
R3
RS
CARD EDGE 
CONNECTOR
PLUG-IN CARD
VIN
GND
OUT
PGD
PWR
TIMER
RETRY
SCL
SMBA
VREF
DIODE
VAUX
SENSE
GATE
VIN_K
UVLO/EN
OVLO
AGND
SDAI
FB
CL
VDD
ADR0
ADR1
ADR2
LM5066H1
VIN
GND
SDAO
R1
MMBT3904
To
Load
Figure 8-21. Recommended Board Connector Design
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SENSE
RESISTOR
RS
VIN_K
SENSE
FROM SYSTEM 
INPUT VOLTAGE
TO DRAIN OF 
MOSFET Q1
HIGH CURRENT PATH
VIN
Figure 8-22. Sense Resistor Connections
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9 Device and Documentation Support
9.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT 
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES 
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER 
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on 
Notifications to register and receive a weekly digest of any product information that has changed. For change 
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight 
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do 
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled 
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may 
be more susceptible to damage because very small parametric changes could cause the device not to meet its published 
specifications.
9.6 Glossary
TI Glossary 
This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2025) to Revision A (December 2025)
Page
•
Changed from Advance Information to Production Data....................................................................................1
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most 
current data available for the designated devices. This data is subject to change without notice and revision of 
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM5066H

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PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2025
PACKAGING INFORMATION
Orderable part number
Status
(1)
Material type
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
(4)
MSL rating/
Peak reflow
(5)
Op temp (°C)
Part marking
(6)
LM5066H1PWPR
Active
Production
HTSSOP (PWP) | 28
2500 | LARGE T&R
-
NIPDAU
Level-3-260C-168 HR
-40 to 125
L5066H1
PLM5066H1PWPR
Active
Preproduction
HTSSOP (PWP) | 28
1 | LARGE T&R
-
Call TI
Call TI
-40 to 125
 
(1) Status:  For more details on status, see our product life cycle.
 
(2) Material type:  When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
 
(3) RoHS values:  Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
 
(4) Lead finish/Ball material:  Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
 
(5) MSL rating/Peak reflow:  The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
 
(6) Part marking:  There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
 
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
 
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
 
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
 
Addendum-Page 1

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www.ti.com
PACKAGE OUTLINE
C
26X 0.65
2X
8.45
28X 0.30
0.17
6.6
6.2 TYP
0.15
0.05
0.25
GAGE PLANE
0 -8
1.2 MAX
2X (0.6)
NOTE 5
2X (0.23)
NOTE 5
5.62
4.92
2.94
2.24
B
4.5
4.3
A
9.8
9.6
NOTE 3
0.75
0.50
(0.15) TYP
PowerPAD   TSSOP - 1.2 mm max height
PWP0028V
SMALL OUTLINE PACKAGE
4230409/A   01/2024
1
14
15
28
0.1
C A B
PIN 1 INDEX
AREA
SEE DETAIL  A
0.1 C
NOTES: 
 
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
    per ASME Y14.5M. 
2. This drawing is subject to change without notice. 
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
    exceed 0.15 mm per side. 
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
 
SEATING
PLANE
TM
PowerPAD is a trademark of Texas Instruments.
A  20
DETAIL A
TYPICAL
SCALE  2.000
THERMAL
PAD
1
14
15
28

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www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
28X (1.5)
28X (0.45)
26X (0.65)
(5.8)
(R0.05) TYP
(3.4)
NOTE 9
(9.7)
NOTE 9
(1.3) TYP
(0.6)
(1.2) TYP
(
0.2) TYP
VIA
(2.94)
(5.62)
PowerPAD   TSSOP - 1.2 mm max height
PWP0028V
SMALL OUTLINE PACKAGE
4230409/A   01/2024
NOTES: (continued)
 
  6. Publication IPC-7351 may have alternate designs. 
  7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
  8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
      numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
      or tented. 
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SYMM
SYMM
1
14
15
28
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
SEE DETAILS
15.000
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED

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www.ti.com
EXAMPLE STENCIL DESIGN
28X (1.5)
28X (0.45)
26X (0.65)
(5.8)
(R0.05) TYP
(5.62)
BASED ON
0.125 THICK
STENCIL
(2.94)
BASED ON
0.125 THICK
STENCIL
PowerPAD   TSSOP - 1.2 mm max height
PWP0028V
SMALL OUTLINE PACKAGE
4230409/A   01/2024
2.48 X 4.75
0.175
2.68 X 5.13
0.15
2.94 X 5.62 (SHOWN)
0.125
3.29 X 6.28
0.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
 
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
      design recommendations.   
12. Board assembly site may have different recommendations for stencil design.
 
TM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
SYMM
SYMM
1
14
15
28
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES

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Last updated 10/2025

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