kernel: migrate CPUID feature detection to cpufeature crate

The kernel currently maintains CPU feature detection using hand-written
CPUID leaf/register/bit checks. This duplicates CPUID definitions,
requires updating multiple locations as new features are added, and is
prone to inconsistencies.

Replace the local CPUID feature machinery with the shared cpufeature
crate, which is auto-generated from the X86-CPUID database and serves as
a single source of truth for CPU feature definitions. Remove features.rs
and the local Feature enum, implement CpuidBackend for Native, SNP, and
TDP, and route feature queries through platform::{cpuid, cpuid_value,
has_cpuid_feature}. Update call sites to use cpufeature leaf descriptors
directly for SMEP, SMAP, CET, XSAVE, TLB, and other CPU features.

Signed-off-by: tanish111 <tanishdesai37@gmail.com>

Author: tanish111

Cargo.lock

@@ -103,6 +103,9 @@ virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev =
 zerocopy = { version = "0.8.2", features = ["derive"] }
 zeroize = { version = "1.8.2", default-features = false }
 
+#Github repos
+cpufeature = { git = "https://github.com/tanish111/cpufeature.git", rev = "4f86e2d062ab8e456566d00db64913caa2f53f33" }
+
 # Verus repos
 verus_builtin = { version = "=0.0.0-2026-04-12-0118", default-features = false }
 verus_builtin_macros = { version = "=0.0.0-2026-04-12-0118", features = ["vpanic"], default-features = false }

Cargo.toml

@@ -16,6 +16,7 @@ doctest = true
 bootdefs.workspace = true
 bootimg.workspace = true
 cpuarch.workspace = true
+cpufeature.workspace = true
 libaproxy = { workspace = true, optional = true }
 elf.workspace = true
 syscall.workspace = true

kernel/Cargo.toml

@@ -5,10 +5,13 @@
 // Author: Joerg Roedel <jroedel@suse.de>
 
 use crate::address::{Address, PhysAddr};
-use crate::cpu::features::{Feature, cpu_has_feat};
+use crate::platform::has_cpuid_feature;
 use core::arch::asm;
 use cpuarch::x86::CR0Flags;
 use cpuarch::x86::CR4Flags;
+use cpufeature::leaves::{
+    CET_SS, X86_FEATURE_PGE, X86_FEATURE_SMAP, X86_FEATURE_SMEP, X86_FEATURE_UMIP,
+};
 
 #[inline]
 pub fn cr0_init() {
@@ -33,25 +36,34 @@ pub fn cr4_init() {
     // All processors that are capable of virtualization will support global
     // page table entries, so there is no reason to support any processor that
     // does not enumerate PGE capability.
-    assert!(cpu_has_feat(Feature::Pge), "CPU does not support PGE");
+    assert!(
+        has_cpuid_feature(&X86_FEATURE_PGE),
+        "CPU does not support PGE"
+    );
 
     cr4.insert(CR4Flags::PGE); // Enable Global Pages
 
     if !cfg!(feature = "nosmep") {
-        assert!(cpu_has_feat(Feature::Smep), "CPU does not support SMEP");
+        assert!(
+            has_cpuid_feature(&X86_FEATURE_SMEP),
+            "CPU does not support SMEP"
+        );
         cr4.insert(CR4Flags::SMEP);
     }
 
     if !cfg!(feature = "nosmap") {
-        assert!(cpu_has_feat(Feature::Smap), "CPU does not support SMAP");
+        assert!(
+            has_cpuid_feature(&X86_FEATURE_SMAP),
+            "CPU does not support SMAP"
+        );
         cr4.insert(CR4Flags::SMAP);
     }
 
-    if cpu_has_feat(Feature::Umip) {
+    if has_cpuid_feature(&X86_FEATURE_UMIP) {
         cr4.insert(CR4Flags::UMIP);
     }
 
-    if cpu_has_feat(Feature::CetSS) {
+    if has_cpuid_feature(&CET_SS) {
         cr4.insert(CR4Flags::CET);
     }
 

kernel/src/cpu/control_regs.rs

@@ -10,7 +10,6 @@ pub mod cpuid;
 pub mod cpuset;
 pub mod efer;
 pub mod extable;
-pub mod features;
 pub mod gdt;
 pub mod idt;
 pub mod ipi;

kernel/src/cpu/features.rs

@@ -6,7 +6,6 @@
 
 extern crate alloc;
 
-use super::features::{Feature, cpu_has_feat};
 use super::gdt::GDT;
 use super::ipi::IpiState;
 use super::isst::Isst;
@@ -40,6 +39,7 @@ use crate::mm::{
     SVSM_SHADOW_STACK_ISST_DF_BASE, SVSM_SHADOW_STACKS_INIT_TASK, SVSM_STACK_IST_DF_BASE,
     virt_to_phys,
 };
+use crate::platform::has_cpuid_feature;
 use crate::platform::{SVSM_PLATFORM, SvsmPlatform};
 use crate::requests::SvsmCaa;
 use crate::sev::ghcb::{GHCB, GhcbPage};
@@ -75,6 +75,7 @@ use core::sync::atomic::AtomicU64;
 use core::sync::atomic::AtomicUsize;
 use core::sync::atomic::Ordering;
 use cpuarch::vmsa::VMSA;
+use cpufeature::leaves::CET_SS;
 
 // PERCPU areas virtual addresses into shared memory
 pub static PERCPU_AREAS: PerCpuAreas = PerCpuAreas::new();
@@ -837,14 +838,14 @@ impl PerCpu {
         // Reserve ranges and initialize allocator for temporary mappings
         self.initialize_vm_ranges()?;
 
-        if cpu_has_feat(Feature::CetSS) {
+        if has_cpuid_feature(&CET_SS) {
             self.allocate_init_shadow_stack()?;
         }
 
         // Allocate per-cpu context switch stack
         self.allocate_context_switch_stack()?;
 
-        if cpu_has_feat(Feature::CetSS) {
+        if has_cpuid_feature(&CET_SS) {
             self.allocate_context_switch_shadow_stack()?;
         }
 
@@ -854,7 +855,7 @@ impl PerCpu {
         // Setup TSS
         self.setup_tss();
 
-        if cpu_has_feat(Feature::CetSS) {
+        if has_cpuid_feature(&CET_SS) {
             // Allocate ISST shadow stacks
             self.allocate_isst_shadow_stacks()?;
 
@@ -869,7 +870,7 @@ impl PerCpu {
 
         // Allocate hypercall pages if running on Hyper-V, unless this is the
         // BSP (where they will be allocated later).
-        if self.shared.cpu_index() != 0 && cpu_has_feat(Feature::HyperV) {
+        if self.shared.cpu_index() != 0 && hyperv::is_hyperv_host() {
             self.allocate_hypercall_pages()?;
         }
 

kernel/src/cpu/mod.rs

@@ -5,13 +5,15 @@
 // Author: Vasant Karasulli <vkarasulli@suse.de>
 
 use crate::cpu::control_regs::{cr0_sse_enable, cr4_osfxsr_enable, cr4_xsave_enable};
-use crate::platform::cpuid;
+use crate::platform::{cpuid, has_cpuid_feature};
 use core::arch::asm;
 use core::arch::x86_64::{_xgetbv, _xsetbv};
 use core::sync::atomic::{AtomicU64, Ordering};
-
-use super::features::{Feature, cpu_has_feat};
-
+use cpufeature::CpuidFeature;
+use cpufeature::leaves::{
+    X86_FEATURE_XMM, X86_FEATURE_XSAVE, X86_FEATURE_XSAVEOPT, XCR0_AVX, XCR0_SSE, XCR0_X87,
+    XSAVE_SZ,
+};
 const XCR0_X87_ENABLE: u64 = 0x1;
 const XCR0_SSE_ENABLE: u64 = 0x2;
 const XCR0_YMM_ENABLE: u64 = 0x4;
@@ -22,7 +24,7 @@ pub const XSAVE_LEGACY_SIZE: u32 = 0x240;
 static SVSM_XCR0: AtomicU64 = AtomicU64::new(XCR0_X87_ENABLE | XCR0_SSE_ENABLE);
 
 fn legacy_sse_enable() {
-    if cpu_has_feat(Feature::Sse1) {
+    if has_cpuid_feature(&X86_FEATURE_XMM) {
         cr4_osfxsr_enable();
         cr0_sse_enable();
     } else {
@@ -40,10 +42,10 @@ fn xcr0_set() {
 }
 
 fn xsave_enable() {
-    if cpu_has_feat(Feature::Xsave) && cpu_has_feat(Feature::XsaveOpt) {
-        if cpu_has_feat(Feature::Xcr0X87)
-            && cpu_has_feat(Feature::Xcr0Sse)
-            && cpu_has_feat(Feature::Xcr0Avx)
+    if has_cpuid_feature(&X86_FEATURE_XSAVE) && has_cpuid_feature(&X86_FEATURE_XSAVEOPT) {
+        if has_cpuid_feature(&XCR0_X87)
+            && has_cpuid_feature(&XCR0_SSE)
+            && has_cpuid_feature(&XCR0_AVX)
         {
             SVSM_XCR0.fetch_or(XCR0_YMM_ENABLE, Ordering::Relaxed);
         }
@@ -75,7 +77,11 @@ pub fn xsave_area_size() -> u32 {
         if xcr0 & (1u64 << bit) == 0 {
             continue;
         }
-        let Some(result) = cpuid(0xd, bit) else {
+        let feature = CpuidFeature {
+            subleaf: bit,
+            ..XSAVE_SZ
+        };
+        let Some(result) = cpuid(&feature) else {
             log::warn!("FP feature {bit:#x} enabled but not present in CPUID");
             continue;
         };