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kernel: use cpufeature crate for CET shadow stack detection
Add the cpufeature dependency and implement CpuidBackend for native and SNP platforms. CET support is now checked via CET_SS instead of manual CPUID bit masking on both platforms. Signed-off-by: tanish111 <tanishdesai37@gmail.com>
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Lines changed: 36 additions & 24 deletions

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Cargo.lock

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Cargo.toml

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@@ -103,6 +103,9 @@ virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev =
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zerocopy = { version = "0.8.2", features = ["derive"] }
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zeroize = { version = "1.8.2", default-features = false }
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#Github repos
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cpufeature = { git = "https://github.com/tanish111/cpufeature.git", rev = "4f86e2d062ab8e456566d00db64913caa2f53f33" }
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# Verus repos
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verus_builtin = { version = "=0.0.0-2026-04-12-0118", default-features = false }
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verus_builtin_macros = { version = "=0.0.0-2026-04-12-0118", features = ["vpanic"], default-features = false }

kernel/Cargo.toml

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@@ -16,6 +16,7 @@ doctest = true
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bootdefs.workspace = true
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bootimg.workspace = true
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cpuarch.workspace = true
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cpufeature.workspace = true
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libaproxy = { workspace = true, optional = true }
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elf.workspace = true
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syscall.workspace = true

kernel/src/platform/native.rs

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@@ -1,7 +1,6 @@
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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) Microsoft Corporation
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// Copyright (c) SUSE LLC
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//
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// Author: Jon Lange <jlange@microsoft.com>
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// Author: Joerg Roedel <jroedel@suse.de>
@@ -12,7 +11,6 @@ use super::PageStateChangeOp;
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use super::PageValidateOp;
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use super::SvsmPlatform;
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use super::capabilities::Caps;
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use super::cpuid;
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use crate::address::{PhysAddr, VirtAddr};
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use crate::console::init_svsm_console;
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use crate::cpu::IrqGuard;
@@ -38,6 +36,8 @@ use cpuarch::x86apic::IcrMessageType;
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use bootdefs::kernel_launch::BLDR_BASE;
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use core::arch::asm;
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use core::mem::MaybeUninit;
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use cpufeature::backend::CpuidBackend;
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use cpufeature::leaves::CPU_VENDORID_1;
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use syscall::GlobalFeatureFlags;
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#[cfg(debug_assertions)]
@@ -59,6 +59,8 @@ impl NativePlatform {
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}
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}
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impl CpuidBackend for NativePlatform {}
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impl SvsmPlatform for NativePlatform {
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#[cfg(test)]
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fn platform_type(&self) -> SvsmPlatformType {
@@ -87,14 +89,10 @@ impl SvsmPlatform for NativePlatform {
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}
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fn get_cpu_vendor(&self) -> CpuVendor {
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if let Some(r) = cpuid(0, 0) {
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match r.edx {
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0x69746e65 => CpuVendor::AMD,
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0x49656e69 => CpuVendor::Intel,
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_ => CpuVendor::Unknown,
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}
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} else {
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CpuVendor::Unknown
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match Self::cpuid_value(&CPU_VENDORID_1) {
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Some(0x6974_6e65) => CpuVendor::AMD,
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Some(0x4965_6e69) => CpuVendor::Intel,
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_ => CpuVendor::Unknown,
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}
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}
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kernel/src/platform/snp.rs

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@@ -58,6 +58,8 @@ use core::arch::x86_64::CpuidResult;
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use core::mem::MaybeUninit;
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use core::ptr;
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use core::sync::atomic::{AtomicU32, Ordering};
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use cpufeature::CpuidFeature;
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use cpufeature::backend::CpuidBackend;
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use syscall::GlobalFeatureFlags;
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static GHCB_IO_DRIVER: GHCBIOPort = GHCBIOPort::new();
@@ -296,20 +298,6 @@ impl SvsmPlatform for SnpPlatform {
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})
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}
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fn cpuid(eax: u32, ecx: u32) -> Option<CpuidResult>
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where
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Self: Sized,
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{
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// If this is an architectural CPUID leaf, then extract the result
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// from the CPUID table. Otherwise, request the value from the
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// hypervisor.
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if (eax >> 28) == 4 {
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current_ghcb().cpuid(eax, ecx).ok()
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} else {
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cpuid_table(eax, ecx)
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}
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}
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unsafe fn write_host_msr(&self, msr: u32, value: u64) {
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current_ghcb()
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.wrmsr(msr, value)
@@ -480,6 +468,22 @@ impl SvsmPlatform for SnpPlatform {
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}
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}
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impl CpuidBackend for SnpPlatform {
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fn cpuid(feature: &CpuidFeature) -> Option<CpuidResult>
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where
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Self: Sized,
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{
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// If this is an architectural CPUID leaf, then extract the result
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// from the CPUID table. Otherwise, request the value from the
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// hypervisor.
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if (feature.leaf >> 28) == 4 {
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current_ghcb().cpuid(feature.leaf, feature.subleaf).ok()
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} else {
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cpuid_table(feature.leaf, feature.subleaf)
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}
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}
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}
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#[derive(Clone, Copy, Debug, Default)]
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pub struct GHCBIOPort {}
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