kernel: migrate CPUID feature detection to cpufeature crate

Replace the hand-rolled CpuFeat/CpuidReg machinery with descriptors
from the external cpufeature crate and route CPUID queries through
CpuidBackend on each platform.
- Add cpufeature as a workspace dependency
- Simplify features.rs to map Feature variants to leaf descriptors
- Remove SvsmPlatform::cpuid; implement CpuidBackend for Native, SNP,
  and TDP instead
- Add platform::cpuid and platform::cpuid_value dispatchers
- Use XSAVE_SZ descriptor in xsave_area_size()

Signed-off-by: tanish111 <tanishdesai37@gmail.com>

Author: tanish111

Cargo.lock

@@ -103,6 +103,9 @@ virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev =
 zerocopy = { version = "0.8.2", features = ["derive"] }
 zeroize = { version = "1.8.2", default-features = false }
 
+#Github repos
+cpufeature = { git = "https://github.com/tanish111/cpufeature.git", rev = "4f86e2d062ab8e456566d00db64913caa2f53f33" }
+
 # Verus repos
 verus_builtin = { version = "=0.0.0-2026-04-12-0118", default-features = false }
 verus_builtin_macros = { version = "=0.0.0-2026-04-12-0118", features = ["vpanic"], default-features = false }

Cargo.toml

@@ -16,6 +16,7 @@ doctest = true
 bootdefs.workspace = true
 bootimg.workspace = true
 cpuarch.workspace = true
+cpufeature.workspace = true
 libaproxy = { workspace = true, optional = true }
 elf.workspace = true
 syscall.workspace = true

kernel/Cargo.toml

@@ -2,173 +2,83 @@
 //
 // Copyright (c) 2022-2023, 2026 SUSE LLC
 //
-// Authors: Joerg Roedel <jroedel@suse.de>
-//          Carlos López <clopez@suse.de>
-
-use core::arch::x86_64::CpuidResult;
-
-use crate::{platform::cpuid, utils::immut_after_init::ImmutAfterInitCell};
-
-/// The CPUID output register for a particular feature
-#[derive(Clone, Copy, Debug)]
-enum CpuidReg {
-    Eax,
-    Ebx,
-    Ecx,
-    Edx,
-}
-
-/// A discoverable CPU feature.
-///
-/// At the moment this type is used for CPUID detection, but it can
-/// be expanded to use other sources of information.
-#[derive(Debug)]
-struct CpuFeat {
-    /// Raw value
-    val: ImmutAfterInitCell<u32>,
-    /// CPUID leaf
-    leaf: u32,
-    /// CPUID subleaf
-    subleaf: u32,
-    /// CPUID output register
-    reg: CpuidReg,
-    /// Bitshift to apply to raw value
-    shift: u8,
-    /// Bitmask to apply to raw value
-    bitsize: u8,
-    /// Expected value after shift + mask
-    expected: u32,
+// Author: Joerg Roedel <jroedel@suse.de>
+// Author: Carlos López <clopez@suse.de>
+
+use cpufeature::CpuidFeature;
+use cpufeature::CpuidRegister;
+use cpufeature::leaves::{
+    CET_SS, INVLPGB_MAX_PAGES, PHYS_ADDR_BITS, PTE_CBIT_POS, X86_FEATURE_PGE, X86_FEATURE_SMAP,
+    X86_FEATURE_SMEP, X86_FEATURE_UMIP, X86_FEATURE_X2APIC, X86_FEATURE_XMM, X86_FEATURE_XSAVE,
+    X86_FEATURE_XSAVEOPT, XCR0_AVX, XCR0_SSE, XCR0_X87,
+};
+
+use crate::platform::cpuid_value;
+
+/// Hyper-V CPUID interface signature (`"Hv#1"`) on leaf `0x40000001`.
+const HYPERV_INTERFACE: CpuidFeature = CpuidFeature {
+    leaf: 0x4000_0001,
+    subleaf: 0,
+    register: CpuidRegister::Eax,
+    shift: 0,
+    width: 32,
+};
+
+/// Discoverable CPU features backed by [`cpufeature`] leaf descriptors.
+#[repr(usize)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Feature {
+    X2Apic,
+    Xsave,
+    Pge,
+    Sse1,
+    Smep,
+    Smap,
+    Umip,
+    CetSS,
+    Xcr0X87,
+    Xcr0Sse,
+    Xcr0Avx,
+    XsaveOpt,
+    HyperV,
+    PhysAddrSizes,
+    InvlpgbMax,
+    Cbit,
 }
 
-impl CpuFeat {
-    /// Create a new feature, indicated by a single bit in the specified
-    /// register in the given CPUID leaf.
-    const fn new_bit(leaf: u32, reg: CpuidReg, bit: u8) -> Self {
-        Self::new(leaf, reg, bit, 1, 1)
-    }
-
-    /// Create a new feature, indicated by the full value of a register
-    /// in the given CPUID leaf.
-    const fn new_u32(leaf: u32, reg: CpuidReg, expected: u32) -> Self {
-        Self::new(leaf, reg, 0, u32::BITS as u8, expected)
-    }
-
-    /// Create a new CPU feature, detected by querying the given CPUID leaf, and applying
-    /// a bitshift and bitmask on the specified output register to compare it to the given
-    /// expected value.
-    const fn new(leaf: u32, reg: CpuidReg, shift: u8, bitsize: u8, expected: u32) -> Self {
-        // This method is only called from const context, so these assertions have no
-        // runtime effect.
-        assert!((shift as u32) < u32::BITS);
-        assert!((bitsize as u32) <= u32::BITS);
-        Self {
-            val: ImmutAfterInitCell::uninit(),
-            leaf,
-            subleaf: 0,
-            reg,
-            shift,
-            bitsize,
-            expected,
-        }
-    }
-
-    /// Create a copy of the given CPU feature, but with the specified
-    /// subleaf.
-    const fn with_subfn(mut self, subleaf: u32) -> Self {
-        self.subleaf = subleaf;
-        self
-    }
-
-    /// Get the CPUID register that corresponds to this feature
-    const fn get_reg(&self, cpuid: &CpuidResult) -> u32 {
-        match self.reg {
-            CpuidReg::Eax => cpuid.eax,
-            CpuidReg::Ebx => cpuid.ebx,
-            CpuidReg::Ecx => cpuid.ecx,
-            CpuidReg::Edx => cpuid.edx,
-        }
-    }
-
-    const fn mask(&self) -> u32 {
-        ((1u64 << self.bitsize) - 1) as u32
-    }
-
-    fn get_or_init(&self) -> u32 {
-        if let Ok(val) = self.val.try_get_inner() {
-            return *val;
+impl Feature {
+    const fn descriptor(self) -> &'static CpuidFeature {
+        match self {
+            Self::X2Apic => &X86_FEATURE_X2APIC,
+            Self::Xsave => &X86_FEATURE_XSAVE,
+            Self::Pge => &X86_FEATURE_PGE,
+            Self::Sse1 => &X86_FEATURE_XMM,
+            Self::Smep => &X86_FEATURE_SMEP,
+            Self::Smap => &X86_FEATURE_SMAP,
+            Self::Umip => &X86_FEATURE_UMIP,
+            Self::CetSS => &CET_SS,
+            Self::Xcr0X87 => &XCR0_X87,
+            Self::Xcr0Sse => &XCR0_SSE,
+            Self::Xcr0Avx => &XCR0_AVX,
+            Self::XsaveOpt => &X86_FEATURE_XSAVEOPT,
+            Self::HyperV => &HYPERV_INTERFACE,
+            Self::PhysAddrSizes => &PHYS_ADDR_BITS,
+            Self::InvlpgbMax => &INVLPGB_MAX_PAGES,
+            Self::Cbit => &PTE_CBIT_POS,
         }
-        let val = cpuid(self.leaf, self.subleaf).map_or(0, |c| self.get_reg(&c));
-        // If init() fails it means the cell got initialized by someone else
-        // concurrently, which is always benign.
-        let _ = self.val.init(val);
-        val
-    }
-
-    /// Gets the raw value of this feature, lazily querying CPUID if
-    /// the value is not cached from a previous query
-    fn get(&self) -> u32 {
-        (self.get_or_init() >> self.shift) & self.mask()
-    }
-
-    /// Checks whether this feature is available by comparing it to
-    /// its expected value, lazily querying CPUID if the value is not
-    /// cached from a previous query
-    fn enabled(&self) -> bool {
-        self.get() == self.expected
     }
 }
 
-/// Macro to generate a CPU feature lookup table
-macro_rules! define_cpu_feats {
-    (
-        $(
-            $variant:ident => $feat_expr:expr
-        ),* $(,)?
-    ) => {
-
-        // Feature enum to use as index
-        #[repr(usize)]
-        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
-        pub enum Feature {
-            $( $variant, )*
-        }
-
-        /// The number of defined features
-        const NUM_FEATS: usize = [ $( stringify!($variant) ),* ].len();
-
-        static CPU_FEATS: [CpuFeat; NUM_FEATS] = [
-            $( $feat_expr, )*
-        ];
-    };
-}
-
-/// Check if the given feature is enabled by comparing it to its expected
-/// value.
+/// Check if the given feature is enabled.
 pub fn cpu_has_feat(feat: Feature) -> bool {
-    // Because of #[repr(usize)], this cast matches the array index perfectly.
-    CPU_FEATS[feat as usize].enabled()
+    match feat {
+        Feature::HyperV => cpuid_value(feat.descriptor()) == Some(0x3123_7648),
+        Feature::PhysAddrSizes | Feature::InvlpgbMax | Feature::Cbit => false,
+        _ => cpuid_value(feat.descriptor()) == Some(1),
+    }
 }
 
-/// Gets the raw value of the given feature
+/// Get the raw CPUID field value for the given feature.
 pub fn cpu_get_feat(feat: Feature) -> u32 {
-    CPU_FEATS[feat as usize].get()
-}
-
-define_cpu_feats! {
-    X2Apic => CpuFeat::new_bit(0x0000_0001, CpuidReg::Ecx, 21),
-    Xsave => CpuFeat::new_bit(0x0000_0001, CpuidReg::Ecx, 26),
-    Pge => CpuFeat::new_bit(0x0000_0001, CpuidReg::Edx, 13),
-    Sse1 => CpuFeat::new_bit(0x0000_0001, CpuidReg::Edx, 25),
-    Smep => CpuFeat::new_bit(0x0000_0007, CpuidReg::Ebx, 7),
-    Smap => CpuFeat::new_bit(0x0000_0007, CpuidReg::Ebx, 20),
-    Umip => CpuFeat::new_bit(0x0000_0007, CpuidReg::Ecx, 2),
-    CetSS => CpuFeat::new_bit(0x0000_0007, CpuidReg::Ecx, 7),
-    Xcr0X87 => CpuFeat::new_bit(0x0000_000d, CpuidReg::Eax, 0),
-    Xcr0Sse => CpuFeat::new_bit(0x0000_000d, CpuidReg::Eax, 1),
-    Xcr0Avx => CpuFeat::new_bit(0x0000_000d, CpuidReg::Eax, 2),
-    XsaveOpt => CpuFeat::new_bit(0x0000_000d, CpuidReg::Eax, 0).with_subfn(1),
-    HyperV => CpuFeat::new_u32(0x40000001, CpuidReg::Eax, 0x31237648),
-    PhysAddrSizes => CpuFeat::new_u32(0x80000008, CpuidReg::Eax, 0),
-    InvlpgbMax => CpuFeat::new(0x80000008, CpuidReg::Edx, 0, u16::BITS as u8, 0),
-    Cbit => CpuFeat::new(0x8000001f, CpuidReg::Ebx, 0, 6, 0),
+    cpuid_value(feat.descriptor()).unwrap_or(0)
 }

kernel/src/cpu/features.rs

@@ -9,6 +9,8 @@ use crate::platform::cpuid;
 use core::arch::asm;
 use core::arch::x86_64::{_xgetbv, _xsetbv};
 use core::sync::atomic::{AtomicU64, Ordering};
+use cpufeature::CpuidFeature;
+use cpufeature::leaves::XSAVE_SZ;
 
 use super::features::{Feature, cpu_has_feat};
 
@@ -75,7 +77,11 @@ pub fn xsave_area_size() -> u32 {
         if xcr0 & (1u64 << bit) == 0 {
             continue;
         }
-        let Some(result) = cpuid(0xd, bit) else {
+        let feature = CpuidFeature {
+            subleaf: bit,
+            ..XSAVE_SZ
+        };
+        let Some(result) = cpuid(&feature) else {
             log::warn!("FP feature {bit:#x} enabled but not present in CPUID");
             continue;
         };

kernel/src/cpu/sse.rs

@@ -156,9 +156,7 @@ fn handle_cpuid(ctx: &mut X86ExceptionContext) -> Result<(), SvsmError> {
 }
 
 fn snp_cpuid(ctx: &mut X86ExceptionContext) -> Result<(), SvsmError> {
-    let cpuid_fn = ctx.regs.rax as u32;
-    let cpuid_subfn = ctx.regs.rcx as u32;
-    let Some(ret) = cpuid_table(cpuid_fn, cpuid_subfn) else {
+    let Some(ret) = cpuid_table(ctx.regs.rax as u32, ctx.regs.rcx as u32) else {
         return Err(VcError::new(ctx, VcErrorType::UnknownCpuidLeaf).into());
     };
 

kernel/src/cpu/vc.rs

@@ -19,9 +19,12 @@ use snp::SnpPlatform;
 use tdp::TdpPlatform;
 
 use core::arch::asm;
-use core::arch::x86_64::{__cpuid_count, CpuidResult};
+use core::arch::x86_64::CpuidResult;
+
 use core::fmt::Debug;
 use core::mem::MaybeUninit;
+use cpufeature::CpuidFeature;
+use cpufeature::backend::CpuidBackend;
 
 use crate::address::{PhysAddr, VirtAddr};
 use crate::boot_params::BootParams;
@@ -181,15 +184,6 @@ pub trait SvsmPlatform: Sync {
         hypercall_pages: &hyperv::HypercallPagesGuard<'_>,
     ) -> hyperv::HvHypercallOutput;
 
-    /// Obtain CPUID using platform-specific tables.
-    fn cpuid(eax: u32, ecx: u32) -> Option<CpuidResult>
-    where
-        Self: Sized,
-    {
-        // SAFETY: CPUID is always safe
-        unsafe { Some(__cpuid_count(eax, ecx)) }
-    }
-
     /// Write a host-owned MSR.
     /// # Safety
     /// The caller must ensure that the requested MSR modification does mot
@@ -368,8 +362,13 @@ macro_rules! platform_method {
 }
 
 #[inline]
-pub fn cpuid(leaf: u32, subleaf: u32) -> Option<CpuidResult> {
-    platform_method!(cpuid, leaf, subleaf)
+pub fn cpuid(feature: &CpuidFeature) -> Option<CpuidResult> {
+    platform_method!(cpuid, feature)
+}
+
+#[inline]
+pub fn cpuid_value(feature: &CpuidFeature) -> Option<u32> {
+    platform_method!(cpuid_value, feature)
 }
 
 pub fn halt() {