Print full command invocation

Author: matth2k

bin/eqmap

@@ -43,7 +43,7 @@ else
     echo "FAMILY=xcup" >> $MKFILE
     echo "PART=xczu3eg-sbva484-1-i" >> $MKFILE
     echo "# flatten design before synthesis, no clock buffers, no IO buffers, no carry logic, no MUXes" >> $MKFILE
-    echo "SYNTH_OPT=-flatten -noclkbuf -noiopad -nocarry -nowidelut -nosrl -ise" >> $MKFILE
+    echo "SYNTH_OPT=-flatten -noclkbuf -noiopad -nocarry -nowidelut -nosrl -nodsp -ise" >> $MKFILE
     echo "YOSYS=yosys # Yosys 0.33 (git sha1 2584903a060)" >> $MKFILE
     echo "XILINX_VIVADO?=\$(realpath \$(dirname \$(which vivado))/..)" >> $MKFILE
     echo "VIVADO=\$(XILINX_VIVADO)/bin/vivado" >> $MKFILE
@@ -67,7 +67,7 @@ else
     echo "	@echo \"synth_xilinx -family \$(FAMILY) \$(SYNTH_OPT)\" >> \$@" >> $MKFILE
     echo "	@echo \"clean -purge\" >> \$@" >> $MKFILE
     echo "	@echo \"splitnets -ports -format _\" >> \$@" >> $MKFILE
-    echo "	@echo \"write_verilog -simple-lhs \$<.yxil\" >> \$@" >> $MKFILE
+    echo "	@echo \"write_verilog -simple-lhs -noattr \$<.yxil\" >> \$@" >> $MKFILE
     echo "" >> $MKFILE
     echo "# This script synthesizes to AND, NOR, XOR, INV, MUXes" >> $MKFILE
     echo "%_synth.ys: %.v" >> $MKFILE

src/bin/eqmap_asic.rs

@@ -97,6 +97,9 @@ fn main() -> std::io::Result<()> {
 
     eprintln!("INFO: ASIC Technology Mapping Optimization with E-Graphs");
 
+    let full_command = std::env::args().collect::<Vec<_>>().join(" ");
+    eprintln!("INFO: {}", full_command);
+
     let mut buf = String::new();
 
     let path: Option<PathBuf> = match args.input {

src/bin/eqmap_fpga.rs

@@ -126,6 +126,9 @@ fn main() -> std::io::Result<()> {
 
     eprintln!("INFO: EqMap (FPGA Technology Mapping w/ E-Graphs)");
 
+    let full_command = std::env::args().collect::<Vec<_>>().join(" ");
+    eprintln!("INFO: {}", full_command);
+
     let mut buf = String::new();
 
     let path: Option<PathBuf> = match args.input {