Fix wire decl for escaped names (#120)

Author: matth2k

src/verilog.rs

@@ -1239,7 +1239,7 @@ impl fmt::Display for SVModule {
         for signal in self.signals.iter() {
             let indent = " ".repeat(level + 2);
             if !already_decl.contains(&signal.name) {
-                writeln!(f, "{}wire {};", indent, signal.name)?;
+                writeln!(f, "{}wire {};", indent, emit_id(signal.name.clone()))?;
             }
         }
         for instance in self.instances.iter() {

verilog/simlib.v

@@ -123,3 +123,25 @@ module MUX (
 );
   assign Y = S ? A : B;
 endmodule
+
+
+module FDRE #(
+    parameter INIT = 0
+) (
+    input  C,
+    input  CE,
+    input  D,
+    input  R,
+    output Q
+);
+  reg q;
+  always @(posedge C) begin
+    if (CE) begin
+      if (R) begin
+        q <= INIT;
+      end else begin
+        q <= D;
+      end
+    end
+  end
+endmodule