Fix netlist rewrite (#219)

Author: matth2k

Cargo.lock

@@ -46,9 +46,9 @@ toml = "0.9.11"
 thiserror = { version = "2.0.16" }
 sv-parser = "0.13.4"
 ctrlc = "3.5.1"
-safety-net = { version = "0.5.4", features = ["graph"] }
+safety-net = { version = "0.5.5", features = ["graph"] }
 good_lp = { version = "1.14.2", optional = true }
-nl-compiler = { version = "0.1.14" }
+nl-compiler = { version = "0.1.15" }
 
 [lints.clippy]
 manual_range_contains = "allow"

Cargo.toml

@@ -552,11 +552,11 @@ impl<I: Instantiable + LogicFunc<L>, L: CircuitLang + LogicCell<I>> LogicMapping
         drop(self);
         drop(mapping);
 
-        let mut new_roots = Vec::new();
+        let mut new_roots = HashSet::new();
 
         for (old, new) in root_pairs {
             if old == new {
-                new_roots.push(new);
+                new_roots.insert(new);
                 continue;
             }
 
@@ -566,14 +566,14 @@ impl<I: Instantiable + LogicFunc<L>, L: CircuitLang + LogicCell<I>> LogicMapping
             }
 
             netlist.replace_net_uses(old, &new)?;
-            new_roots.push(new);
+            new_roots.insert(new);
         }
 
-        netlist.clean()?;
+        netlist.retain(&mut new_roots)?;
 
         netlist.rename_nets(|_, i| format_id!("__{i}__"))?;
 
-        Ok(new_roots)
+        Ok(new_roots.into_iter().collect())
     }
 }
 

src/netlist.rs

@@ -0,0 +1,81 @@
+// RUN: eqmap_fpga %s --assert-sat --no-retime -k 4 | FileCheck %s
+
+module rewrite_bug (
+    clk,
+    rst,
+    a,
+    y
+);
+  wire _0_;
+  input a;
+  wire a;
+  input clk;
+  wire clk;
+  wire p;
+  wire q;
+  input rst;
+  wire rst;
+  output y;
+  wire y;
+  LUT2 #(
+      .INIT(4'h5)
+  ) _1_ (
+      .I0(q),
+      .I1(p),
+      .O (_0_)
+  );
+  FDRE #(
+      .INIT(1'hx)
+  ) _2_ (
+      .C (clk),
+      .CE(1'h1),
+      .D (a),
+      .Q (q),
+      .R (rst)
+  );
+  FDRE #(
+      .INIT(1'hx)
+  ) _3_ (
+      .C (clk),
+      .CE(1'h1),
+      .D (q),
+      .Q (p),
+      .R (1'h0)
+  );
+  FDRE #(
+      .INIT(1'hx)
+  ) _4_ (
+      .C (clk),
+      .CE(1'h1),
+      .D (_0_),
+      .Q (y),
+      .R (rst)
+  );
+
+  // CHECK: FDRE #(
+  // CHECK:   .INIT(1'bx)
+  // CHECK: ) __4__ (
+  // CHECK:   .D(a),
+  // CHECK:   .C(clk),
+  // CHECK:   .CE(1'b1),
+  // CHECK:   .R(rst),
+  // CHECK:   .Q(__0__)
+  // CHECK: );
+  // CHECK: FDRE #(
+  // CHECK:   .INIT(1'bx)
+  // CHECK: ) __5__ (
+  // CHECK:   .D(__3__),
+  // CHECK:   .C(clk),
+  // CHECK:   .CE(1'b1),
+  // CHECK:   .R(rst),
+  // CHECK:   .Q(__1__)
+  // CHECK: );
+  // CHECK: LUT1 #(
+  // CHECK:   .INIT(2'b01)
+  // CHECK: ) __7__ (
+  // CHECK:   .I0(__0__),
+  // CHECK:   .O(__3__)
+  // CHECK: );
+  // CHECK: assign y = __1__;
+
+endmodule