Dangling Reference Error

[danielpenas42]

I was running the .sh file after reflattening the file for a second time and got dangling reference error. I will attach the mk, sh and .v file. Some are in txt as it wont let me attach it otherwise. Also this is the errror message that I'm getting:

INFO: stop_reason = "Saturated"
INFO: extract_time = 0.036986775
INFO: build_time = 58.208419244000005
INFO: input_size = 443
INFO: input_contains_gates = false
INFO: num_inputs = 228
INFO: num_outputs = 161
INFO: num_classes = 5835
INFO: num_nodes = 92557
INFO: num_iterations = 48
INFO: saturated = true
INFO: 
INFO: [circuit_stats.before]
INFO: lut_count = 168
INFO: reg_count = 0
INFO: depth = 5
INFO: 
INFO: [circuit_stats.before.lut_distribution]
INFO: 1 = 1
INFO: 2 = 24
INFO: 3 = 11
INFO: 4 = 9
INFO: 5 = 39
INFO: 6 = 84
INFO: 
INFO: [circuit_stats.after]
INFO: lut_count = 164
INFO: reg_count = 0
INFO: depth = 5
INFO: 
INFO: [circuit_stats.after.lut_distribution]
INFO: 1 = 1
INFO: 2 = 15
INFO: 3 = 11
INFO: 4 = 6
INFO: 5 = 38
INFO: 6 = 93
INFO: Writing output to Verilog...
Error: Custom { kind: Other, error: DanglingReference([Net { identifier: Identifier { name: "reinst_386_O", id_type: Normal }, data_type: FourState }]) }
[███████████████████████████████████░░░░░░░░░░░░░░░░░░░░░░░░░] 38/64 iterations
[██████████████████████████░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░] 109774/250000 nodes
[██░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░] ⠒ 24s      `


[dma_ahbmst_flat.txt](https://github.com/user-attachments/files/25892539/dma_ahbmst_flat.txt)
[run.sh](https://github.com/user-attachments/files/25892538/run.sh)
[run.txt](https://github.com/user-attachments/files/25892537/run.txt)

[matth2k]

@danielpenas42 I don't think the files attached properly, because the links got caught in the code segment. Link is not found: https://github.com/user-attachments/files/25892539/dma_ahbmst_flat.txt

[matth2k]

I can't get the error to reproduce on my end. But I think I have a clue what's going wrong

1. Notice the net being complained as still being referenced is reinst_386_O. This means clean() wants to delete an object we just created to replace an old node.

If we look at the code where clean() gets called, we can see that all the root replacement cells get put into a vec called new_roots

        let mut new_roots = Vec::new();

        for (old, new) in root_pairs {
            if old == new {
                new_roots.push(new);
                continue;
            }

            if !old.is_an_input() && old.is_top_level_output() {
                let id = old.get_identifier() + "_overwritten".into();
                old.as_net_mut().set_identifier(id);
            }

            netlist.replace_net_uses(old, &new)?;
            new_roots.push(new);
        }

        netlist.clean()?;

        netlist.rename_nets(|_, i| format_id!("__{i}__"))?;

        Ok(new_roots)

My hunch is that clean() tries to delete something that we want to return in new_roots, hence the error. The only problem is that I cannot confirm this, as I cannot reproduce the bug.

If you change (at netlist.v:572)

        netlist.clean()?;

        netlist.rename_nets(|_, i| format_id!("__{i}__"))?;

        Ok(new_roots)

to

        drop(new_roots);
        netlist.clean()?;

        netlist.rename_nets(|_, i| format_id!("__{i}__"))?;

        Ok(Vec::new())

Does the error go away? If so, that kind of confirms my guess is correct.

[matth2k]

I was able to make a mini test case to show the bug. Using eqmap_fpga --no-retime gives the same error on this input:

module bug (
    clk,
    rst,
    a,
    y
);
  wire _0_;
  input a;
  wire a;
  input clk;
  wire clk;
  wire p;
  wire q;
  input rst;
  wire rst;
  output y;
  wire y;
  LUT2 #(
      .INIT(4'h5)
  ) _1_ (
      .I0(q),
      .I1(p),
      .O (_0_)
  );
  FDRE #(
      .INIT(1'hx)
  ) _2_ (
      .C (clk),
      .CE(1'h1),
      .D (a),
      .Q (q),
      .R (rst)
  );
  FDRE #(
      .INIT(1'hx)
  ) _3_ (
      .C (clk),
      .CE(1'h1),
      .D (q),
      .Q (p),
      .R (1'h0)
  );
  FDRE #(
      .INIT(1'hx)
  ) _4_ (
      .C (clk),
      .CE(1'h1),
      .D (_0_),
      .Q (y),
      .R (rst)
  );
endmodule

Basically, the roots are inter-dependent. Let's say we re-synthesize partitions A, B, C. And A uses B and C. If after re-synthesis A no longer uses B, B tries to get cleaned but the return statement still tries to return a reference to portion B.

[matth2k]

One solution could be passing a "watchlist" to the safety-net clean() API. Meaning you do netlist.clean(&mut watchlist), where watchlist is a set of DrivenNet<I> you would like to hold on to if they are not deleted.

It's just annoying to add a whole nother API call for this kinda niche task.

[matth2k]

@danielpenas42 Can you check that #219 fixes the issue for you?

[danielpenas42]

I will try right now