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Fix inverted logic
1 parent 0fbd74f commit cdb6f44

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3 files changed

+4
-3
lines changed

3 files changed

+4
-3
lines changed

lib/Echidna/SourceAnalysis/Slither.hs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,4 +185,5 @@ emptySlitherInfo = SlitherInfo mempty mempty mempty mempty mempty [] [] []
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isEmptySlitherInfo :: Maybe SlitherInfo -> Bool
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isEmptySlitherInfo (Just (SlitherInfo _ _ _ _ _ [] [] [])) = True
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isEmptySlitherInfo Nothing = True
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isEmptySlitherInfo _ = False

lib/Echidna/UI.hs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,7 @@ ui vm dict initialCorpus cliSelectedContract = do
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, timeStarted = now
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, timeStopped = Nothing
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, now = now
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, slitherSucceeded = isEmptySlitherInfo env.slitherInfo
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, slitherSucceeded = not $ isEmptySlitherInfo env.slitherInfo
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, fetchedContracts = mempty
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, fetchedSlots = mempty
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, fetchedDialog = B.dialog (Just $ str " Fetched contracts/slots ") Nothing 80

lib/Echidna/UI/Widgets.hs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -228,8 +228,8 @@ slitherWidget
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:: Bool
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-> Widget Name
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slitherWidget slitherSucceeded = if slitherSucceeded
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then alert (str "No Slither in use")
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else success (str "Slither succeeded")
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then success (str "Slither succeeded")
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else alert (str "No Slither in use!")
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outOf :: Int -> Int -> Widget n
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outOf n m =

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