Internal signals don't work after Verilator update

[acw1251]

pyverilator finds internal signals by parsing VL_SIG* lines in an .h file generated by verilator. The most recent version of verilator looks like it doesn't use the VL_SIG* macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:

CData/*7:0*/ parent_module__DOT__in_reg;

pyverilator should also look for this format as well.

[acw1251]

It looks like this is the Verilator commit that introduced this bug:
verilator/verilator@21a380d
Until pyverilator is updated to support this new format, you can revert to Verilator v4.020 or earlier to get rid of this problem.