cleanup

Author: gabizon103

apps/frisc/harness/run.sh

@@ -7,4 +7,4 @@ cargo run --bin filament ../src/cpu.fil --library ../../.. --backend calyx --dis
 
 python expected.py
 
-# rm top.err top.out top.json frisc.futil
+rm top.err top.out top.json frisc.futil

apps/frisc/harness/tests.py

@@ -5,6 +5,9 @@
 
 test1 = """
 addi x1 x0 2
+addi x0 x0 0
+addi x0 x0 0
+addi x0 x0 0
 sw x1 0(x1)
 """
 

apps/frisc/harness/top.futil

@@ -8,9 +8,11 @@ component main (@clk clk: 1, @reset reset: 1, @go go: 1) -> () {
     cpu = CPU();
 
     pc_reg = std_reg(32);
+    rf_reg = std_reg(32);
   }
   wires {
     static<1> group read_iram {
+      cpu.go = 1'd1;
       iram.addr0 = cpu.pc;
 
       cpu.instr = iram.read_data;
@@ -31,17 +33,23 @@ component main (@clk clk: 1, @reset reset: 1, @go go: 1) -> () {
       pc_reg.in = cpu.pc;
       pc_reg.write_en = %0 ? 1'd1;
     }
+    
+    static<1> group reg_rf {
+      rf_reg.in = cpu.rfDataOut;
+      rf_reg.write_en = %0 ? 1'd1;
+    }
 
     cpu.pcin = cpu.nextpc;
-    cpu.rfDataIn = cpu.rfDataOut;
+    cpu.rfDataIn = rf_reg.out;
   }
   control {
     static seq {
-      static repeat 6 {
+      static repeat 10 {
         static par {
           read_iram;
           write_res;
           reg_pc;
+          reg_rf;
         } 
       }
     }

apps/frisc/harness/top_2_64.futil

@@ -0,0 +1,57 @@
+import "frisc.futil";
+import "primitives/memories/comb.futil";
+
+component main (@clk clk: 1, @reset reset: 1, @go go: 1) -> () {
+  cells {
+    @external iram = comb_mem_d1(32,2,32);
+    @external res = comb_mem_d1(32,64,32);
+    cpu = CPU();
+
+    pc_reg = std_reg(32);
+    rf_reg = std_reg(32);
+  }
+  wires {
+    static<1> group read_iram {
+      cpu.go = 1'd1;
+      iram.addr0 = cpu.pc;
+
+      cpu.instr = iram.read_data;
+      // cpu.dataIn = dram.read_data;
+
+      // dram.addr0 = cpu.memAddr;
+      // dram.write_data = cpu.memData;
+      // dram.write_mask = cpu.memWriteMask;
+    }
+
+    static<1> group write_res {
+      res.addr0 = cpu.memAddr;
+      res.write_data = cpu.memData;
+      res.write_en = cpu.isStore;
+    }
+
+    static<1> group reg_pc {
+      pc_reg.in = cpu.pc;
+      pc_reg.write_en = %0 ? 1'd1;
+    }
+    
+    static<1> group reg_rf {
+      rf_reg.in = cpu.rfDataOut;
+      rf_reg.write_en = %0 ? 1'd1;
+    }
+
+    cpu.pcin = cpu.nextpc;
+    cpu.rfDataIn = rf_reg.out;
+  }
+  control {
+    static seq {
+      static repeat 6 {
+        static par {
+          read_iram;
+          write_res;
+          reg_pc;
+          reg_rf;
+        } 
+      }
+    }
+  }
+}

apps/frisc/harness/top_5_64.futil

@@ -0,0 +1,57 @@
+import "frisc.futil";
+import "primitives/memories/comb.futil";
+
+component main (@clk clk: 1, @reset reset: 1, @go go: 1) -> () {
+  cells {
+    @external iram = comb_mem_d1(32,5,32);
+    @external res = comb_mem_d1(32,64,32);
+    cpu = CPU();
+
+    pc_reg = std_reg(32);
+    rf_reg = std_reg(32);
+  }
+  wires {
+    static<1> group read_iram {
+      cpu.go = 1'd1;
+      iram.addr0 = cpu.pc;
+
+      cpu.instr = iram.read_data;
+      // cpu.dataIn = dram.read_data;
+
+      // dram.addr0 = cpu.memAddr;
+      // dram.write_data = cpu.memData;
+      // dram.write_mask = cpu.memWriteMask;
+    }
+
+    static<1> group write_res {
+      res.addr0 = cpu.memAddr;
+      res.write_data = cpu.memData;
+      res.write_en = cpu.isStore;
+    }
+
+    static<1> group reg_pc {
+      pc_reg.in = cpu.pc;
+      pc_reg.write_en = %0 ? 1'd1;
+    }
+    
+    static<1> group reg_rf {
+      rf_reg.in = cpu.rfDataOut;
+      rf_reg.write_en = %0 ? 1'd1;
+    }
+
+    cpu.pcin = cpu.nextpc;
+    cpu.rfDataIn = rf_reg.out;
+  }
+  control {
+    static seq {
+      static repeat 10 {
+        static par {
+          read_iram;
+          write_res;
+          reg_pc;
+          reg_rf;
+        } 
+      }
+    }
+  }
+}