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9,Towards mechanized verification of Verilog equivalence checking,Michalis Pardalos (Imperial College London); Laura Pozzi (Università della Svizzera italiana (USI) Lugano); John Wickerson (Imperial College London),Session 1,false,
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13,Arbitrary Bitwidth Rewrite Verification via Equality Saturation,Luigi Rinaldi and John Wickerson (Imperial College London); Yann Herklotz (EPFL); Samuel Coward (Intel Corporation),Session 1,false,
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14,Incremental Conversion of SVA Properties to Synthesizable Hardware,Amelia Dobis (Princeton University); Fabian Schuiki (Sifive); Mae Milano (Princeton University),Session 1,false,
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6,Rust-Based Domain-Specific Language for SFQ Circuit Design,Mebuki Oishi and Sun Tanaka (The University of Toyko); Shinya Takamaeda-Yamazaki (The University of Tokyo),Session 2,false,
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6,Rust-Based Domain-Specific Language for SFQ Circuit Design,Mebuki Oishi and Sun Tanaka (University of Tokyo); Shinya Takamaeda-Yamazaki (University of Tokyo),Session 2,false,
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16,Wisteria: a modern and general Structural Description Language,Victor Miquel (ENS Paris),Session 2,false,
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10,High-Level Synthesis with Linear Types,Izumi Tanaka; Ken Sakayori; Shinya Takamaeda-Yamazaki; and Naoki Kobayashi (The University of Tokyo),Session 3,false,
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10,High-Level Synthesis with Linear Types,Izumi Tanaka; Ken Sakayori; Shinya Takamaeda-Yamazaki; and Naoki Kobayashi (University of Tokyo),Session 3,false,
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5,Hardware.jl — An MLIR-based Julia HLS Flow (Work in Progress),"Benedict Short, Ian McInerney, and John Wickerson (Imperial College London)",Session 3,false,
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7,Choc: A Communication Toolkit to Help Hardware Module Drivers Navigate SoC Architectures,Mattis Hasler (Barkhausen Institut),Session 4,false,
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11,Advanced Communication Pattern Support for Hardware Accelerators,"Guillem López-Paradís (BSC & UPC); Nazerke Turtayeva (UC Santa Barbara); Guy Wilks (CMU); Tianrui Wei (University of California, Berkeley); Vicenç Beltran (BSC); Adrià Armejach and Miquel Moreto (BSC & UPC); Jonathan Balkind (jbalkind@ucsb.edu)",Session 4,false,
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