Various queues: benchmark verilog from the wild against our Calyx-generated code

[anshumanmohan]

This is sorta a pet issue of @polybeandip's and I want to put it down as a medium/low priority item!

We have at this point implemented a number of queue structures in Calyx, but we should not forget that many of these came from relatively recent research papers and themselves shipped with Verilog code. Other people's Verilog is not doubt going to be hard to understand and maintain (...and thus the sales pitch of Calyx itself) but that stuff could potentially be hand-optimized by the OG authors and could be blazing fast. Even if we suspect it is not all that good, it would be nice for us to be able to quantitatively say that our Calyx code beat them or was comparable to them.

A biggish challenge will be simply figuring out what the wild Verilog is even doing. Once we know that, we can tweak our Calyx implementations to match that behavior. Then we can benchmark.

[KabirSamsi]

I think this should go hand-in-hand with #46 as a consideration of how we represent/compile to different queues with our DSL.