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testing marlin wide support
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+34
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protocols/src/sim.rs

Lines changed: 34 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ impl Simulation for VerilatorSim {}
2020
pub mod tests {
2121
use crate::yosys::*;
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use baa::{BitVecOps, BitVecValue};
23+
use marlin_verilator::dynamic::DynamicVerilatedModel;
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use marlin_verilator::*;
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use patronus::sim::Simulator;
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use std::path::PathBuf;
@@ -41,19 +42,48 @@ pub mod tests {
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.unwrap();
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let conf = VerilatedModelConfig::default();
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let _dut = runtime
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let (clk, rcon, inp, out_1, out_2) = ("clk", "rcon", "in", "out_1", "out_2");
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let mut dut = runtime
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.create_dyn_model(
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"expand_key_128",
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"../examples/tinyaes128/aes_128.v",
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&[
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// you should be able to derive these from the struct
50-
("in", 127, 0, PortDirection::Input),
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("out_1", 127, 0, PortDirection::Output),
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("out_2", 127, 0, PortDirection::Output),
52+
(clk, 0, 0, PortDirection::Input),
53+
(rcon, 7, 0, PortDirection::Input),
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(inp, 127, 0, PortDirection::Input),
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(out_1, 127, 0, PortDirection::Output),
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(out_2, 127, 0, PortDirection::Output),
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],
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conf,
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)
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.unwrap();
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62+
let step = |dut: &mut DynamicVerilatedModel| {
63+
dut.pin(clk, 1u8).unwrap();
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dut.eval();
65+
dut.pin(clk, 0u8).unwrap();
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};
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68+
// execute an expand_key
69+
let inp_value = [0u32; 4];
70+
dut.pin(inp, &inp_value).unwrap();
71+
dut.pin(rcon, 1u8).unwrap(); // rcon is a constant for the circuit
72+
dut.pin(clk, 0u8).unwrap();
73+
dut.eval();
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step(&mut dut);
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76+
let inp_value_2 = [11u32; 4];
77+
dut.pin(inp, &inp_value_2).unwrap(); // X
78+
dut.eval();
79+
let out_1_val = dut.read(out_1).unwrap();
80+
println!("out_1 = {out_1_val:?}");
81+
step(&mut dut);
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83+
dut.pin(inp, &inp_value_2).unwrap(); // X
84+
dut.eval();
85+
let out_2_val = dut.read(out_2).unwrap();
86+
println!("out_2 = {out_2_val:?}");
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}
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#[test]

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