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[Monitor + Interp] Wishbone subordinate example (#193)
* Add example Wishbone Verilog files * Add Wishbone subordinate protocol file * Fix Protocol so that interpreter works * add todo * Add TODOs to Wishbone protocol * Add comments * Update Verilator test-bench so that it works on arm64 Macs * Fix bugs in C++ testbench based on slides * Gitignore VCD files * Edit Wishbone protocols to also inspect LED state * Update wishbone.tx * More changes to test-bench + monitor * Update two versions of wishbone.prot to be in sync * fix typo * Update monitor version of Wishbone protocol * Update transaction file for interpreter * [Interp] Add transaction info to assert_eq error messages * Comments' * Add new --display-hex CLI flag to interpreter * Format nullary protocols better in the error msg * [skip ci] Remove outdated comment about interpreter only accepting 1 Verilog file * Standardize the two versions of the Wishbone protocol * Remove LED from monitor Wishbone protocol * Fix typo in monitor WB prot * Make interpreter version of WB protocol same as monitor's * Add comments to wishbone.tx * Add comments to wishbone.prot (both versions)
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‎monitor/tests/wishbone/reqwalker.vcd‎

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‎monitor/tests/wishbone/wishbone.err‎

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‎monitor/tests/wishbone/wishbone.out‎

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// trace 0
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trace {
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read(0, 0);
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write(0, 0);
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read(0, 3);
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read(0, 5);
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read(0, 7);
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read(0, 9);
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read(0, 11);
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read(0, 0);
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write(0, 0);
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read(0, 3);
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read(0, 5);
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read(0, 7);
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read(0, 9);
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read(0, 11);
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read(0, 0);
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}

‎monitor/tests/wishbone/wishbone.prot‎

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// ARGS: --wave wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk
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// Wishbone B4 (Pipeline mode) subordinate
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struct WBSubordinate {
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// Cycle is high anytime an active pipeline session is occurring
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in i_cyc: u1,
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// Strobe is high when there is a request to the subordinate
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// (akin to Valid in AXI-Lite, i.e. they indicate the manager
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// has something to transfer)
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in i_stb: u1,
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// Write-enable (true for write-requests)
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in i_we: u1,
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// Address of the request
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in i_addr: u1,
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// Data to be written
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in i_data: u32,
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// Response from the subordinate, indicating that the request
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// has been fulfilled.
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out o_ack: u1,
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// True on any cycle when the subordinate can't accept requests
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// False when a request can be accepted
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// (i.e. the opposite of Ready in AXI-Lite)
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out o_stall: u1,
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// Data returned by the subordinate to the manager
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// This is valid only when ACK is true
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out o_data: u32,
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}
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// Both cyc & stb are low when the subordinate is low,
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// everything else is DontCare
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#[idle]
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prot idle<DUT: WBSubordinate>() {
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DUT.i_cyc := 1'b0;
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DUT.i_stb := 1'b0;
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DUT.i_we := X;
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DUT.i_addr := X;
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DUT.i_data := X;
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step();
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}
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// Writes a `data` value to the subordinate.
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// Wishbone says to hold all request signals while stalled (stall=1),
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// i.e. when the subordinate is busy processing a previous request.
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prot write<DUT: WBSubordinate>(in addr: u1, in data: u32) {
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DUT.i_cyc := 1'b1;
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DUT.i_stb := 1'b1;
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DUT.i_we := 1'b1;
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DUT.i_addr := addr;
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DUT.i_data := data;
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// Wait till the subordinate Acks
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// Note that in the Verilog, after the subordinate acks,
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// `o_stall` is assigned combinationally (`o_stall = busy && i_we`),
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// so we don't need another while-loop to wait for `stall` to become 0
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while (DUT.o_ack == 1'b0) {
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step();
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}
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// Data is updated combinationally in the same cycle as the ack,
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// so no separate cycle for data transfer is needed
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assert_eq(DUT.o_data, data);
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// Set other inputs to DontCare
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// Note that the waveform produced by their C++ test-bench keeps
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// `cyc` and `stb` high, so we don't set `cyc` and `stb` to 0 here
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DUT.i_cyc := X;
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DUT.i_stb := X;
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DUT.i_we := X;
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DUT.i_addr := X;
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DUT.i_data := X;
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step();
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}
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// Reads a value from the subordinate
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// (the `data` is conveyed via output parameters)
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prot read<DUT: WBSubordinate>(in addr: u1, out data: u32) {
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DUT.i_cyc := 1'b1;
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DUT.i_stb := 1'b1;
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DUT.i_we := 1'b0;
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DUT.i_addr := addr;
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DUT.i_data := X;
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// Wait for subordinate to Ack
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// (When we're reading, the write-enable is always 0,
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// but in the Verilog, `stall` is a boolean AND of `i_we` and another
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// signal, so `stall` is always 0 when we're reading, so we don't
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// need another while-loop to wait for `stall` to become 0)
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while (DUT.o_ack == 1'b0) {
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step();
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}
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// Data is updated combinationally in the same cycle as the ack,
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// so no separate cycle for data transfer is needed
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assert_eq(DUT.o_data, data);
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// Set other inputs to DontCare
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// Note that the waveform produced by their C++ test-bench keeps
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// `cyc` and `stb` high, so we don't set `cyc` and `stb` to 0 here
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DUT.i_cyc := X;
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DUT.i_stb := X;
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DUT.i_we := X;
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DUT.i_addr := X;
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step();
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}

‎protocols/tests/wishbone/.gitignore‎

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obj_dir/*
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reqwalker_tb
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*.vcd

‎protocols/tests/wishbone/Makefile‎

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################################################################################
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##
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## Filename: Makefile
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##
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## Project: Verilog Tutorial Example file
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##
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## Purpose: Builds the Verilator request-walker bus slave example
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##
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## Targets:
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##
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## The (default) or all target will build a verilator simulation for the
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## Request Walker.
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##
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## clean Removes all build products
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Written and distributed by Gisselquist Technology, LLC
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##
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## This program is hereby granted to the public domain.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.
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##
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################################################################################
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##
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##
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.PHONY: all
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all: reqwalker_tb
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VERILATOR=verilator
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VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
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VINC := $(VERILATOR_ROOT)/include
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obj_dir/Vreqwalker.cpp: reqwalker.v
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$(VERILATOR) --trace -Wall -cc reqwalker.v
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obj_dir/Vreqwalker__ALL.a: obj_dir/Vreqwalker.cpp
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make --no-print-directory -C obj_dir -f Vreqwalker.mk
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reqwalker_tb: reqwalker.cpp obj_dir/Vreqwalker__ALL.a
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g++ -I$(VINC) -I obj_dir $(VINC)/verilated.cpp \
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$(VINC)/verilated_vcd_c.cpp \
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$(VINC)/verilated_threads.cpp reqwalker.cpp \
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obj_dir/Vreqwalker__ALL.a -o reqwalker_tb
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.PHONY: clean
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clean:
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rm -rf obj_dir/ reqwalker_tb reqwalker.vcd reqwalker_cvr/ reqwalker_prf/

‎protocols/tests/wishbone/reqwalker.cpp‎

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: redqalker.cpp
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//
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// Project: Verilog Tutorial Example file
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//
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// Purpose: This is an example Verilator test bench driver file reqwalker
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// module.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Written and distributed by Gisselquist Technology, LLC
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//
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// This program is hereby granted to the public domain.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <stdlib.h>
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#include "Vreqwalker.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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// Required by Verilator when not using SystemC
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double sc_time_stamp() { return 0; }
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int tickcount = 0;
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Vreqwalker *tb;
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VerilatedVcdC *tfp;
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void tick(void) {
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tickcount++;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10 - 2);
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tb->i_clk = 1;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10);
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tb->i_clk = 0;
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tb->eval();
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if (tfp) {
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tfp->dump(tickcount * 10 + 5);
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tfp->flush();
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}
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}
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unsigned wb_read(unsigned a) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 0;
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tb->eval(); // update o_stall, which depends combinationally on i_we
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tb->i_addr= a;
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// Make the request
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while(tb->o_stall)
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tick();
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tick();
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tb->i_stb = 0;
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// Wait for the ACK
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while(!tb->o_ack)
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tick();
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// Idle the bus, and read the response
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tb->i_cyc = 0;
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return tb->o_data;
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}
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void wb_write(unsigned a, unsigned v) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 1;
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tb->eval(); // update o_stall, which depends combinationally on i_we
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tb->i_addr= a;
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tb->i_data= v;
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// Make the bus request
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while(tb->o_stall)
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tick();
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tick();
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tb->i_stb = 0;
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// Wait for the acknowledgement
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while(!tb->o_ack)
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tick();
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// Idle the bus and return
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tb->i_cyc = tb->i_stb = 0;
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}
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int main(int argc, char **argv) {
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int last_led, last_state = 0, state = 0;
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// Call commandArgs first!
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Verilated::commandArgs(argc, argv);
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// Instantiate our design
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tb = new Vreqwalker;
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// Generate a trace
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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tb->trace(tfp, 99);
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tfp->open("reqwalker.vcd");
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last_led = tb->o_led;
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// Read from the current state
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printf("Initial state is: 0x%02x\n",
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wb_read(0));
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for(int cycle=0; cycle<2; cycle++) {
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// Wait five clocks
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for(int i=0; i<5; i++)
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tick();
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// Start the LEDs cycling
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wb_write(0,0);
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tick();
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while((state = wb_read(0))!=0) {
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if ((state != last_state)
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||(tb->o_led != last_led)) {
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printf("%6d: State #%2d ",
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tickcount, state);
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for(int j=0; j<6; j++) {
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if(tb->o_led & (1<<j))
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printf("O");
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else
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printf("-");
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} printf("\n");
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}
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last_state = state;
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last_led = tb->o_led;
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// Idle cycle between reads so the VCD captures i_stb=0,
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// making each transaction visible as a separate event to the monitor
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tb->i_cyc = tb->i_stb = 0;
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tick();
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}
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}
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tfp->close();
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delete tfp;
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delete tb;
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}

‎protocols/tests/wishbone/reqwalker.sby‎

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[tasks]
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cvr
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prf
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[options]
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cvr: mode cover
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prf: mode prove
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[engines]
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smtbmc
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[script]
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read -formal reqwalker.v
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prep -top reqwalker
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[files]
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reqwalker.v

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