[lang] add module declarations and rename struct to interface #203
Description
Currently, struct is used to define the pins of the design under test. Protocols (prot) are defined over a particular struct.
I propose to switch the nondescript struct to two new concepts:
- Interfaces define only the pins required for a particular protocol. Protocols are parametric over interfaces. Existing structs can be turned into interfaces by replacing
structwithinterface. - Modules represent actual Verilog modules. This is a new feature. Modules serve as a way of connecting abstract interfaces to concrete Verilog implementations. A module can implement several interfaces. Moreover, additional pins can be defined and labeled. We might also want to introduce a feature to rename/bind interface pins.
Module example for a aes submodule:
// src: https://github.com/cucapra/protocols/blob/e3afb5bc8623916097c19fa5fd94694a857b6157/examples/tinyaes128/aes128_expand_key.prot#L2C1-L7C2
interface ExpandKey128 {
in input: u128,
out output: u128,
out output_delayed: u128,
}
// this is the new part which binds our interface to [the verilog](https://github.com/cucapra/protocols/blob/e3afb5bc8623916097c19fa5fd94694a857b6157/examples/tinyaes128/aes_128.v#L59):
module expand_key_128 : ExpandKey128 {
in clk: Clock, // <- new special type "Clock" which is only allowed in `module` declaration
in `in` = ExpandKey128.input, // renaming; we also need to find a way to express identifiers that are also keywords
out out_1 = ExpandKey128.output_delayed,
out out_2 = ExpandKey128.output,
}
I am not 100% happy with the syntax, but something like this would make it easier to interface with actual Verilog designs.