TODO.md

To Do

• Byte Address Memory
  • Create the new data memory module
  • Add the MemWriteCtr
  • l signal based on funct3 when the memory is completed
  • Add into pipelined cpu
  • Test instruction
• Paramaterised MUXs
• Implement lui
• Change PCSel logic to new on for pipelinig
• Test reference program
  • on the single cycle cpu
  • on the pipelined cpu
• Cache Memory
  • Add Cache to single cycle
• Memory Mapping??
  • Change pc to 12 bits
• Add stalling to hazard unit
• Add data fowarding
• Include the .vcd results from successful runs of the programs
• Finalise version of the f1 program