0.3.0

This is a semver-compatible re-release of 0.2.2.

0.2.2 - yanked

This version contains a few minor breaking changes from 0.2.1. These are only surface-level changes, and can be fixed with minimal effort.

Version 0.3.0 is identical to the yanked version 0.2.2, except that it adheres to cargo's modified SemVer rule which states that the pre-0.x.y breaking changes should still bump the minor version.

Thanks to h33p for reporting this issue (#27)

• Add Target::read/write_register support (to support single register accesses) #22 (thomashk0)
• Update Target::resume API to replace raw &mut dyn Iterator with a functionally identical concrete Actions iterator.
• Mark the StopReason enum as non-exhaustive, allowing further types to be added without being considered "breaking changes"
• Add StopReason::Signal(u8) variant, to send arbitrary signal codes #19 (mchesser)
• New arch implementations:
  • Add partial RISC-V support (only integer ISA at the moment) #21 (thomashk0)
  • Add i386 (x86) support #23 (jamcleod)
  • Add 32-bit PowerPC support #25 (jamcleod)

0.2.1

• Add x86_86 support #11 (jamcleod)
• Add Mips and Mips64 support #13 (starfleetcadet75)
• Documentation improvements
  • Document PC adjustment requirements in Target::resume
  • Add docs on handling non-fatal invalid memory reads/writes in Target::read/write_addrs.