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| 1 | +# Copyright (c) 2026, Marin Radic, Harvey Mudd College and Eclipse Foundation |
| 2 | +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 |
| 3 | + |
| 4 | +# UDB Architecture Configuration for the CV32E40X v0.10.0, a configuration of the CORE-V project. |
| 5 | +# Manual: https://github.com/openhwgroup/cv32e40x/tree/main/docs/user_manual |
| 6 | +# Default parameters: RV32=RV32I, M_EXT=M, A_EXT=A_NONE, B_EXT=B_NONE, X_EXT=0, |
| 7 | +# NUM_MHPMCOUNTERS=1, PMA_NUM_REGIONS=0 (no explicit PMA regions), |
| 8 | +# PMP is not implemented (no PMP CSRs). |
| 9 | +--- |
| 10 | +$schema: config_schema.json# |
| 11 | +kind: architecture configuration |
| 12 | +type: fully configured |
| 13 | +name: cv32e40x_rv32imc |
| 14 | +description: CV32E40X v0.10.0 (CORE-V security) - RV32IMC default configuration (A_EXT=NONE, B_EXT=NONE, X_EXT=0) |
| 15 | +implemented_extensions: # VERIFIED against User Manual (Introduction) |
| 16 | + - { name: I, version: "= 2.1" } |
| 17 | + - { name: M, version: "= 2.0" } |
| 18 | + - { name: C, version: "= 2.0" } |
| 19 | + - { name: Zca, version: "= 1.0.0" } |
| 20 | + - { name: Zcb, version: "= 1.0.0" } # VERIFIED -- always enabled per User Manual, Introduction |
| 21 | + - { name: Zcmp, version: "= 1.0.0" } # VERIFIED -- always enabled per User Manual, Introduction |
| 22 | + - { name: Zcmt, version: "= 1.0.0" } # VERIFIED -- always enabled per User Manual, Introduction |
| 23 | + - { name: Zkt, version: "= 1.0.0" } # VERIFIED -- always enabled per User Manual, Introduction; data-independent execution latency |
| 24 | + - { name: Zicsr, version: "= 2.0" } |
| 25 | + - { name: Zifencei, version: "= 2.0" } |
| 26 | + - { name: Zicntr, version: "= 2.0" } |
| 27 | + - { name: Sm, version: "= 1.12.0" } # VERIFIED -- references Priv spec v20211203 (v1.12) |
| 28 | + |
| 29 | +params: |
| 30 | + # XLEN parameters (VERIFIED -- User Manual, Introduction; RV32I base ISA) |
| 31 | + MXLEN: 32 |
| 32 | + PHYS_ADDR_WIDTH: 32 # VERIFIED -- 32-bit addressing, no virtual memory |
| 33 | + |
| 34 | + # MISA (VERIFIED -- User Manual, Control and Status Registers) |
| 35 | + MUTABLE_MISA_M: false # VERIFIED -- M bit hardwired based on M_EXT parameter; not writable at runtime |
| 36 | + MUTABLE_MISA_C: false # VERIFIED -- C bit always hardwired to 1 |
| 37 | + MISA_CSR_IMPLEMENTED: true # VERIFIED -- MISA CSR (0x301) in CSR map |
| 38 | + |
| 39 | + # endianness (VERIFIED -- User Manual, Introduction: little-endian architecture) |
| 40 | + M_MODE_ENDIANNESS: little |
| 41 | + |
| 42 | + # trap/exception behavior (VERIFIED -- User Manual, Exceptions and Interrupts) |
| 43 | + TRAP_ON_ECALL_FROM_M: true # VERIFIED -- ecall always generates Environment call from M-Mode exception |
| 44 | + TRAP_ON_EBREAK: true # VERIFIED -- ebreak generates Breakpoint exception |
| 45 | + TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true # VERIFIED -- User Manual, Exceptions and Interrupts: illegal instruction raised for unimplemented instructions |
| 46 | + TRAP_ON_RESERVED_INSTRUCTION: true # VERIFIED -- undefined encodings raise illegal instruction exception |
| 47 | + TRAP_ON_UNIMPLEMENTED_CSR: true # VERIFIED -- reads/writes to unimplemented CSRs raise illegal instruction exception |
| 48 | + TRAP_ON_ILLEGAL_WLRL: false # VERIFIED -- WARL fields silently mask writes; no illegal-value trap |
| 49 | + |
| 50 | + # MTVAL reporting (VERIFIED -- User Manual, Control and Status Registers, mtval: WARL(0x0) hardwired to 0) |
| 51 | + REPORT_VA_IN_MTVAL_ON_BREAKPOINT: false |
| 52 | + REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: false |
| 53 | + REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: false |
| 54 | + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: false |
| 55 | + REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: false |
| 56 | + REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: false |
| 57 | + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: false |
| 58 | + REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: false |
| 59 | + MTVAL_WIDTH: 32 # 32-bit field, RO hardwired to 0 |
| 60 | + |
| 61 | + # Misaligned load/store support (VERIFIED -- User Manual, Load Store Unit) |
| 62 | + MISALIGNED_LDST: true # VERIFIED -- misaligned accesses supported in hardware for Main memory regions (two bus transactions) |
| 63 | + MISALIGNED_LDST_EXCEPTION_PRIORITY: low # VERIFIED -- no misaligned exception in main memory; I/O raises access fault (code 5/7) |
| 64 | + MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 0 # VERIFIED -- two separate bus transactions, no atomicity guarantee |
| 65 | + MISALIGNED_SPLIT_STRATEGY: custom # VERIFIED -- lowest address transaction performed first (User Manual, Load Store Unit) |
| 66 | + |
| 67 | + # CSR / implementation IDs (VERIFIED -- User Manual, Control and Status Registers) |
| 68 | + ARCH_ID_VALUE: 0x00000014 # VERIFIED -- marchid = 0x14 (decimal 20) per CSR doc reset value 0x0000_0014 |
| 69 | + IMP_ID_VALUE: 0x0 # VERIFIED -- mimpid = 0x0 with mimpid_patch_i=0 (default); MAJOR=0, MINOR=0, PATCH=0 |
| 70 | + VENDOR_ID_BANK: 0xC # VERIFIED -- mvendorid[31:7] = 0xC (OpenHW JEDEC bank 13); CSR reset value 0x0000_0602 |
| 71 | + VENDOR_ID_OFFSET: 0x2 # VERIFIED -- mvendorid[6:0] = 0x2; CSR reset value 0x0000_0602 |
| 72 | + CONFIG_PTR_ADDRESS: 0 # VERIFIED -- mconfigptr hardwired to 0x0 (CSR doc reset value 0x0000_0000) |
| 73 | + |
| 74 | + # MTVEC (VERIFIED -- User Manual, Control and Status Registers, mtvec CLIC==0 section) |
| 75 | + MTVEC_MODES: [0, 1] # VERIFIED -- MODE[1:0] WARL(0x0, 0x1); 0=non-vectored CLINT, 1=vectored CLINT |
| 76 | + MTVEC_ACCESS: rw |
| 77 | + MTVEC_ILLEGAL_WRITE_BEHAVIOR: custom # VERIFIED -- MODE[1] hardwired 0, MODE[0] writable; only values 0/1 retained |
| 78 | + MTVEC_BASE_ALIGNMENT_VECTORED: 128 # VERIFIED -- User Manual csr-mtvec: BASE[31:7] WARL (writable), BASE[6:2] WARL(0x0); RTL CSR_BASIC_MTVEC_MASK=0xFFFFFF81 (bit 7 writable); 2^7 = 128-byte alignment |
| 79 | + MTVEC_BASE_ALIGNMENT_DIRECT: 128 # same 128-byte alignment constraint applies in direct mode |
| 80 | + |
| 81 | + # Sm params |
| 82 | + PRECISE_SYNCHRONOUS_EXCEPTIONS: true # VERIFIED -- User Manual, Exceptions and Interrupts: "All exceptions are precise" |
| 83 | + MARCHID_IMPLEMENTED: true # VERIFIED -- marchid CSR (0xF12) in CSR map |
| 84 | + MIMPID_IMPLEMENTED: true # VERIFIED -- mimpid CSR (0xF13) in CSR map |
| 85 | + PMA_GRANULARITY: 2 # VERIFIED -- pma.rst: word_addr_low/high hold address bits[33:2]; PMA region boundaries are 4-byte (word) aligned; 2^2 = 4 bytes |
| 86 | + NUM_PMP_ENTRIES: 0 # VERIFIED -- no pmpcfg/pmpaddr CSRs in CSR map; PMP not implemented in CV32E40X |
| 87 | + |
| 88 | + # Zcmt params (VERIFIED -- User Manual, Control and Status Registers, jvt section) |
| 89 | + JVT_BASE_TYPE: mask # VERIFIED -- bits[31:6] writable via WARL mask; 64-byte aligned |
| 90 | + JVT_READ_ONLY: false # VERIFIED -- jvt is writable (URW per CSR map) |
| 91 | + JVT_BASE_MASK: 0x7FFFFFC0 # VERIFIED -- jvt BASE[31:6] writable (bit 31 excluded per UDB RV32 schema constraint) |
| 92 | + |
| 93 | + # Zicntr params |
| 94 | + TIME_CSR_IMPLEMENTED: true # VERIFIED -- time/timeh CSRs (0xC01/0xC81) listed in CSR map; shadow of time_i input |
| 95 | + |
| 96 | + # HPM Counters (VERIFIED -- User Manual, Performance Counters) |
| 97 | + # NUM_MHPMCOUNTERS=1 (default) -- only mhpmcounter3 active; counters 4-31 hardwired to 0 |
| 98 | + HPM_EVENTS: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] # VERIFIED -- events 0-15 per User Manual, Performance Counters event table |
| 99 | + HPM_COUNTER_EN: # VERIFIED -- NUM_MHPMCOUNTERS=1; only mhpmcounter3 active; others read-only zero |
| 100 | + [ |
| 101 | + false, # index 0 (CY -- must be false per UDB schema) |
| 102 | + false, # index 1 (TM -- must be false per UDB schema) |
| 103 | + false, # index 2 (IR -- must be false per UDB schema) |
| 104 | + true, # index 3 (MHPMCOUNTER3 -- only active counter with NUM_MHPMCOUNTERS=1) |
| 105 | + false, # 4 |
| 106 | + false, |
| 107 | + false, |
| 108 | + false, # 7 |
| 109 | + false, |
| 110 | + false, |
| 111 | + false, |
| 112 | + false, |
| 113 | + false, |
| 114 | + false, |
| 115 | + false, |
| 116 | + false, # 8..15 |
| 117 | + false, |
| 118 | + false, |
| 119 | + false, |
| 120 | + false, |
| 121 | + false, |
| 122 | + false, |
| 123 | + false, |
| 124 | + false, # 16..23 |
| 125 | + false, |
| 126 | + false, |
| 127 | + false, |
| 128 | + false, |
| 129 | + false, |
| 130 | + false, |
| 131 | + false, |
| 132 | + false, # 24..31 (unimplemented) |
| 133 | + ] |
| 134 | + MCOUNTINHIBIT_IMPLEMENTED: true # VERIFIED -- mcountinhibit CSR (0x320) in CSR map; inhibit bits for mcycle/minstret/mhpmcounterX |
| 135 | + |
| 136 | + COUNTINHIBIT_EN: # VERIFIED -- User Manual, Performance Counters: bit 0=mcycle, bit 2=minstret, bit X=mhpmcounterX |
| 137 | + [ |
| 138 | + true, # index 0 (MCYCLE inhibit -- supported) |
| 139 | + false, # index 1 (TM -- always false per UDB) |
| 140 | + true, # index 2 (MINSTRET inhibit -- supported) |
| 141 | + true, # index 3 (MHPMCOUNTER3 inhibit -- supported) |
| 142 | + false, # 4 |
| 143 | + false, |
| 144 | + false, |
| 145 | + false, # 7 |
| 146 | + false, |
| 147 | + false, |
| 148 | + false, |
| 149 | + false, |
| 150 | + false, |
| 151 | + false, |
| 152 | + false, |
| 153 | + false, # 8..15 |
| 154 | + false, |
| 155 | + false, |
| 156 | + false, |
| 157 | + false, |
| 158 | + false, |
| 159 | + false, |
| 160 | + false, |
| 161 | + false, # 16..23 |
| 162 | + false, |
| 163 | + false, |
| 164 | + false, |
| 165 | + false, |
| 166 | + false, |
| 167 | + false, |
| 168 | + false, |
| 169 | + false, # 24..31 (unimplemented) |
| 170 | + ] |
| 171 | + MCOUNTENABLE_EN: # VERIFIED -- CV32E40X has no U/S mode; mcounteren is WARL(0x0) hardwired; no counter is delegatable |
| 172 | + [ |
| 173 | + false, |
| 174 | + false, |
| 175 | + false, |
| 176 | + false, |
| 177 | + false, |
| 178 | + false, |
| 179 | + false, |
| 180 | + false, |
| 181 | + false, |
| 182 | + false, |
| 183 | + false, |
| 184 | + false, |
| 185 | + false, |
| 186 | + false, |
| 187 | + false, |
| 188 | + false, |
| 189 | + false, |
| 190 | + false, |
| 191 | + false, |
| 192 | + false, |
| 193 | + false, |
| 194 | + false, |
| 195 | + false, |
| 196 | + false, |
| 197 | + false, |
| 198 | + false, |
| 199 | + false, |
| 200 | + false, |
| 201 | + false, |
| 202 | + false, |
| 203 | + false, |
| 204 | + false, |
| 205 | + ] |
| 206 | +# end |
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