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Description
The idea of preferential using op1Reg
for targetReg
for move/copy semantic intrinsics as it done in #40124 should be extended to x86 and more intrinsics on arm64 as pointed out by @CarolEidt and @tannergooding and @kunalspathak
For example, on Arm64 these could be potentially optimized:
Vector64/128.GetElement(0)
AdvSimd.Extract(vec, 0)
AdvSimd.ExtractVector64(upper, lower, 0)
AdvSimd.ExtractVector128(upper, lower, 0)
category:cq
theme:vector-codegen
skill-level:intermediate
cost:medium
impact:medium
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