diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index c772b74fb9b0b7..5beef545daadcd 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -725,6 +725,8 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI_VL, W("EnableAVX512V RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v1, W("EnableAVX10v1"), 1, "Allows AVX10v1+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v2, W("EnableAVX10v2"), 0, "Allows AVX10v2+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNIINT8, W("EnableAVXVNNIINT8"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNIINT16, W("EnableAVXVNNIINT16"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableFMA, W("EnableFMA"), 1, "Allows FMA+ hardware intrinsics to be disabled") diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index 31947520b27948..ea3be7add6d370 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -94,34 +94,40 @@ enum CORINFO_InstructionSet InstructionSet_GFNI=44, InstructionSet_GFNI_V256=45, InstructionSet_GFNI_V512=46, - InstructionSet_X86Base_X64=47, - InstructionSet_SSE_X64=48, - InstructionSet_SSE2_X64=49, - InstructionSet_SSE3_X64=50, - InstructionSet_SSSE3_X64=51, - InstructionSet_SSE41_X64=52, - InstructionSet_SSE42_X64=53, - InstructionSet_AVX_X64=54, - InstructionSet_AVX2_X64=55, - InstructionSet_AES_X64=56, - InstructionSet_BMI1_X64=57, - InstructionSet_BMI2_X64=58, - InstructionSet_FMA_X64=59, - InstructionSet_LZCNT_X64=60, - InstructionSet_PCLMULQDQ_X64=61, - InstructionSet_POPCNT_X64=62, - InstructionSet_AVXVNNI_X64=63, - InstructionSet_X86Serialize_X64=64, - InstructionSet_AVX512F_X64=65, - InstructionSet_AVX512BW_X64=66, - InstructionSet_AVX512CD_X64=67, - InstructionSet_AVX512DQ_X64=68, - InstructionSet_AVX512VBMI_X64=69, - InstructionSet_AVX10v1_X64=70, - InstructionSet_AVX10v1_V512_X64=71, - InstructionSet_AVX10v2_X64=72, - InstructionSet_AVX10v2_V512_X64=73, - InstructionSet_GFNI_X64=74, + InstructionSet_AVXVNNIINT8=47, + InstructionSet_AVXVNNIINT8_V512=48, + InstructionSet_AVXVNNIINT16=49, + InstructionSet_AVXVNNIINT16_V512=50, + InstructionSet_X86Base_X64=51, + InstructionSet_SSE_X64=52, + InstructionSet_SSE2_X64=53, + InstructionSet_SSE3_X64=54, + InstructionSet_SSSE3_X64=55, + InstructionSet_SSE41_X64=56, + InstructionSet_SSE42_X64=57, + InstructionSet_AVX_X64=58, + InstructionSet_AVX2_X64=59, + InstructionSet_AES_X64=60, + InstructionSet_BMI1_X64=61, + InstructionSet_BMI2_X64=62, + InstructionSet_FMA_X64=63, + InstructionSet_LZCNT_X64=64, + InstructionSet_PCLMULQDQ_X64=65, + InstructionSet_POPCNT_X64=66, + InstructionSet_AVXVNNI_X64=67, + InstructionSet_X86Serialize_X64=68, + InstructionSet_AVX512F_X64=69, + InstructionSet_AVX512BW_X64=70, + InstructionSet_AVX512CD_X64=71, + InstructionSet_AVX512DQ_X64=72, + InstructionSet_AVX512VBMI_X64=73, + InstructionSet_AVX10v1_X64=74, + InstructionSet_AVX10v1_V512_X64=75, + InstructionSet_AVX10v2_X64=76, + InstructionSet_AVX10v2_V512_X64=77, + InstructionSet_GFNI_X64=78, + InstructionSet_AVXVNNIINT8_X64=79, + InstructionSet_AVXVNNIINT16_X64=80, #endif // TARGET_AMD64 #ifdef TARGET_X86 InstructionSet_X86Base=1, @@ -170,34 +176,40 @@ enum CORINFO_InstructionSet InstructionSet_GFNI=44, InstructionSet_GFNI_V256=45, InstructionSet_GFNI_V512=46, - InstructionSet_X86Base_X64=47, - InstructionSet_SSE_X64=48, - InstructionSet_SSE2_X64=49, - InstructionSet_SSE3_X64=50, - InstructionSet_SSSE3_X64=51, - InstructionSet_SSE41_X64=52, - InstructionSet_SSE42_X64=53, - InstructionSet_AVX_X64=54, - InstructionSet_AVX2_X64=55, - InstructionSet_AES_X64=56, - InstructionSet_BMI1_X64=57, - InstructionSet_BMI2_X64=58, - InstructionSet_FMA_X64=59, - InstructionSet_LZCNT_X64=60, - InstructionSet_PCLMULQDQ_X64=61, - InstructionSet_POPCNT_X64=62, - InstructionSet_AVXVNNI_X64=63, - InstructionSet_X86Serialize_X64=64, - InstructionSet_AVX512F_X64=65, - InstructionSet_AVX512BW_X64=66, - InstructionSet_AVX512CD_X64=67, - InstructionSet_AVX512DQ_X64=68, - InstructionSet_AVX512VBMI_X64=69, - InstructionSet_AVX10v1_X64=70, - InstructionSet_AVX10v1_V512_X64=71, - InstructionSet_AVX10v2_X64=72, - InstructionSet_AVX10v2_V512_X64=73, - InstructionSet_GFNI_X64=74, + InstructionSet_AVXVNNIINT8=47, + InstructionSet_AVXVNNIINT8_V512=48, + InstructionSet_AVXVNNIINT16=49, + InstructionSet_AVXVNNIINT16_V512=50, + InstructionSet_X86Base_X64=51, + InstructionSet_SSE_X64=52, + InstructionSet_SSE2_X64=53, + InstructionSet_SSE3_X64=54, + InstructionSet_SSSE3_X64=55, + InstructionSet_SSE41_X64=56, + InstructionSet_SSE42_X64=57, + InstructionSet_AVX_X64=58, + InstructionSet_AVX2_X64=59, + InstructionSet_AES_X64=60, + InstructionSet_BMI1_X64=61, + InstructionSet_BMI2_X64=62, + InstructionSet_FMA_X64=63, + InstructionSet_LZCNT_X64=64, + InstructionSet_PCLMULQDQ_X64=65, + InstructionSet_POPCNT_X64=66, + InstructionSet_AVXVNNI_X64=67, + InstructionSet_X86Serialize_X64=68, + InstructionSet_AVX512F_X64=69, + InstructionSet_AVX512BW_X64=70, + InstructionSet_AVX512CD_X64=71, + InstructionSet_AVX512DQ_X64=72, + InstructionSet_AVX512VBMI_X64=73, + InstructionSet_AVX10v1_X64=74, + InstructionSet_AVX10v1_V512_X64=75, + InstructionSet_AVX10v2_X64=76, + InstructionSet_AVX10v2_V512_X64=77, + InstructionSet_GFNI_X64=78, + InstructionSet_AVXVNNIINT8_X64=79, + InstructionSet_AVXVNNIINT16_X64=80, #endif // TARGET_X86 }; @@ -371,6 +383,10 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_AVX10v2_V512_X64); if (HasInstructionSet(InstructionSet_GFNI)) AddInstructionSet(InstructionSet_GFNI_X64); + if (HasInstructionSet(InstructionSet_AVXVNNIINT8)) + AddInstructionSet(InstructionSet_AVXVNNIINT8_X64); + if (HasInstructionSet(InstructionSet_AVXVNNIINT16)) + AddInstructionSet(InstructionSet_AVXVNNIINT16_X64); #endif // TARGET_AMD64 #ifdef TARGET_X86 #endif // TARGET_X86 @@ -569,6 +585,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_GFNI); if (resultflags.HasInstructionSet(InstructionSet_GFNI_X64) && !resultflags.HasInstructionSet(InstructionSet_GFNI)) resultflags.RemoveInstructionSet(InstructionSet_GFNI_X64); + if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_X64)) + resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT8); + if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_X64) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8)) + resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT8_X64); + if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_X64)) + resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT16); + if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_X64) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16)) + resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT16_X64); if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base)) resultflags.RemoveInstructionSet(InstructionSet_SSE); if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE)) @@ -683,6 +707,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE)) resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX)) @@ -811,6 +843,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512)) resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_V512)) + resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE)) resultflags.RemoveInstructionSet(InstructionSet_Vector128); if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX)) @@ -1047,6 +1087,18 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "GFNI_V256"; case InstructionSet_GFNI_V512 : return "GFNI_V512"; + case InstructionSet_AVXVNNIINT8 : + return "AVXVNNIINT8"; + case InstructionSet_AVXVNNIINT8_X64 : + return "AVXVNNIINT8_X64"; + case InstructionSet_AVXVNNIINT8_V512 : + return "AVXVNNIINT8_V512"; + case InstructionSet_AVXVNNIINT16 : + return "AVXVNNIINT16"; + case InstructionSet_AVXVNNIINT16_X64 : + return "AVXVNNIINT16_X64"; + case InstructionSet_AVXVNNIINT16_V512 : + return "AVXVNNIINT16_V512"; #endif // TARGET_AMD64 #ifdef TARGET_X86 case InstructionSet_X86Base : @@ -1141,6 +1193,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "GFNI_V256"; case InstructionSet_GFNI_V512 : return "GFNI_V512"; + case InstructionSet_AVXVNNIINT8 : + return "AVXVNNIINT8"; + case InstructionSet_AVXVNNIINT8_V512 : + return "AVXVNNIINT8_V512"; + case InstructionSet_AVXVNNIINT16 : + return "AVXVNNIINT16"; + case InstructionSet_AVXVNNIINT16_V512 : + return "AVXVNNIINT16_V512"; #endif // TARGET_X86 default: @@ -1224,6 +1284,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_Gfni: return InstructionSet_GFNI; case READYTORUN_INSTRUCTION_Gfni_V256: return InstructionSet_GFNI_V256; case READYTORUN_INSTRUCTION_Gfni_V512: return InstructionSet_GFNI_V512; + case READYTORUN_INSTRUCTION_AvxVnniInt8: return InstructionSet_AVXVNNIINT8; + case READYTORUN_INSTRUCTION_AvxVnniInt8_V512: return InstructionSet_AVXVNNIINT8_V512; + case READYTORUN_INSTRUCTION_AvxVnniInt16: return InstructionSet_AVXVNNIINT16; + case READYTORUN_INSTRUCTION_AvxVnniInt16_V512: return InstructionSet_AVXVNNIINT16_V512; #endif // TARGET_AMD64 #ifdef TARGET_X86 case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base; @@ -1269,6 +1333,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_Gfni: return InstructionSet_GFNI; case READYTORUN_INSTRUCTION_Gfni_V256: return InstructionSet_GFNI_V256; case READYTORUN_INSTRUCTION_Gfni_V512: return InstructionSet_GFNI_V512; + case READYTORUN_INSTRUCTION_AvxVnniInt8: return InstructionSet_AVXVNNIINT8; + case READYTORUN_INSTRUCTION_AvxVnniInt8_V512: return InstructionSet_AVXVNNIINT8_V512; + case READYTORUN_INSTRUCTION_AvxVnniInt16: return InstructionSet_AVXVNNIINT16; + case READYTORUN_INSTRUCTION_AvxVnniInt16_V512: return InstructionSet_AVXVNNIINT16_V512; #endif // TARGET_X86 default: diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 7d81d32a8deb33..59aeebac35d15b 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -37,11 +37,11 @@ #include -constexpr GUID JITEEVersionIdentifier = { /* 7139df75-63b2-4610-9a53-f9a86f474db8 */ - 0x7139df75, - 0x63b2, - 0x4610, - {0x9a, 0x53, 0xf9, 0xa8, 0x6f, 0x47, 0x4d, 0xb8} +constexpr GUID JITEEVersionIdentifier = { /* 16edf70b-d4d0-44c5-9ebc-a9d6898119a5 */ + 0x16edf70b, + 0xd4d0, + 0x44c5, + {0x9e, 0xbc, 0xa9, 0xd6, 0x89, 0x81, 0x19, 0xa5} }; #endif // JIT_EE_VERSIONING_GUID_H diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 56a5f9ab99e12c..6ff979209a8cd4 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -66,6 +66,10 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_RiscV64Base=56, READYTORUN_INSTRUCTION_Zba=57, READYTORUN_INSTRUCTION_Zbb=58, + READYTORUN_INSTRUCTION_AvxVnniInt8=59, + READYTORUN_INSTRUCTION_AvxVnniInt8_V512=60, + READYTORUN_INSTRUCTION_AvxVnniInt16=61, + READYTORUN_INSTRUCTION_AvxVnniInt16_V512=62, }; diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index a00d57962d757b..e7f54a70deb29d 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -812,6 +812,10 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { FIRST_NI_GFNI, LAST_NI_GFNI }, { FIRST_NI_GFNI_V256, LAST_NI_GFNI_V256 }, { FIRST_NI_GFNI_V512, LAST_NI_GFNI_V512 }, + { NI_Illegal, NI_Illegal }, // AVXVNNIINT8 + { NI_Illegal, NI_Illegal }, // AVXVNNIINT8_V512 + { NI_Illegal, NI_Illegal }, // AVXVNNIINT16 + { NI_Illegal, NI_Illegal }, // AVXVNNIINT16_V512 { FIRST_NI_X86Base_X64, LAST_NI_X86Base_X64 }, { FIRST_NI_SSE_X64, LAST_NI_SSE_X64 }, { FIRST_NI_SSE2_X64, LAST_NI_SSE2_X64 }, @@ -840,6 +844,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // AVX10v2_X64 { NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64 { NI_Illegal, NI_Illegal }, // GFNI_X64 + { NI_Illegal, NI_Illegal }, // AVXVNNIINT8_X64 + { NI_Illegal, NI_Illegal }, // AVXVNNIINT16_X64 #elif defined (TARGET_ARM64) { FIRST_NI_ArmBase, LAST_NI_ArmBase }, { FIRST_NI_AdvSimd, LAST_NI_AdvSimd }, diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index 6988d11debe332..bd381069237031 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -411,6 +411,8 @@ RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL, "EnableAVX512VBMI_VL", RELEASE_CONFIG_INTEGER(EnableAVX10v1, "EnableAVX10v1", 1) // Allows AVX10v1+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableAVX10v2, "EnableAVX10v2", 1) // Allows AVX10v2+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableAVXVNNI, "EnableAVXVNNI", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled +RELEASE_CONFIG_INTEGER(EnableAVXVNNIINT8, "EnableAVXVNNIINT8", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled +RELEASE_CONFIG_INTEGER(EnableAVXVNNIINT16, "EnableAVXVNNIINT16", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableBMI1, "EnableBMI1", 1) // Allows BMI1+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableBMI2, "EnableBMI2", 1) // Allows BMI2+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableFMA, "EnableFMA", 1) // Allows FMA+ hardware intrinsics to be disabled diff --git a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs index f552e32731ace1..f54a075816cda4 100644 --- a/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs +++ b/src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs @@ -85,6 +85,8 @@ private static class XArchIntrinsicConstants public const int Vpclmulqdq = 0x200000; public const int Avx10v2 = 0x400000; public const int Gfni = 0x800000; + public const int AvxVnniInt8 = 0x1000000; + public const int AvxVnniInt16 = 0x2000000; public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) { @@ -154,6 +156,14 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags) builder.AddSupportedInstructionSet("avx10v2"); if (((flags & Avx10v2) != 0) && ((flags & Avx512) != 0)) builder.AddSupportedInstructionSet("avx10v2_v512"); + if ((flags & AvxVnniInt8) != 0) + builder.AddSupportedInstructionSet("avxvnniint8"); + if (((flags & AvxVnniInt8) != 0) && ((flags & Avx512) != 0)) + builder.AddSupportedInstructionSet("avxvnniint8_v512"); + if ((flags & AvxVnniInt16) != 0) + builder.AddSupportedInstructionSet("avxvnniint16"); + if (((flags & AvxVnniInt16) != 0) && ((flags & Avx512) != 0)) + builder.AddSupportedInstructionSet("avxvnniint16_v512"); if ((flags & Gfni) != 0) { builder.AddSupportedInstructionSet("gfni"); @@ -235,6 +245,12 @@ public static int FromInstructionSet(InstructionSet instructionSet) InstructionSet.X64_GFNI_X64 => Gfni, InstructionSet.X64_GFNI_V256 => (Gfni | Avx), InstructionSet.X64_GFNI_V512 => (Gfni | Avx512), + InstructionSet.X64_AVXVNNIINT8 => AvxVnniInt8, + InstructionSet.X64_AVXVNNIINT8_X64 => AvxVnniInt8, + InstructionSet.X64_AVXVNNIINT8_V512 => (AvxVnniInt8 | Avx512), + InstructionSet.X64_AVXVNNIINT16 => AvxVnniInt16, + InstructionSet.X64_AVXVNNIINT16_X64 => AvxVnniInt16, + InstructionSet.X64_AVXVNNIINT16_V512 => (AvxVnniInt16 | Avx512), // Baseline ISAs - they're always available InstructionSet.X64_SSE => 0, diff --git a/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs b/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs index de972aced7c565..debc5f1d1f1ff4 100644 --- a/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs +++ b/src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs @@ -366,6 +366,13 @@ public bool ComputeInstructionSetFlags(int maxVectorTBitWidth, _supportedInstructionSets.Add("vpclmul_v512"); } + if (_supportedInstructionSets.Any(iSet => iSet.Contains("avx10v2_v512"))) + { + // AvxVnniInt8 and AvxVnniInt16 512 bit should also be enabled + _supportedInstructionSets.Add("avxvnniint8_v512"); + _supportedInstructionSets.Add("avxvnniint16_v512"); + } + if (_supportedInstructionSets.Any(iSet => iSet.Contains("avx"))) { // These ISAs should automatically extend to 256-bit if diff --git a/src/coreclr/tools/Common/InstructionSetHelpers.cs b/src/coreclr/tools/Common/InstructionSetHelpers.cs index f9e9361fb462c4..83e48ba1856c26 100644 --- a/src/coreclr/tools/Common/InstructionSetHelpers.cs +++ b/src/coreclr/tools/Common/InstructionSetHelpers.cs @@ -233,6 +233,10 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("vpclmul_v512"); optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2"); optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2_v512"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avxvnniint8"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avxvnniint8_v512"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avxvnniint16"); + optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avxvnniint16_v512"); optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("gfni_v512"); } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index 2adcd571b64bcc..6f3792c3a08b9a 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -69,6 +69,10 @@ public enum ReadyToRunInstructionSet RiscV64Base=56, Zba=57, Zbb=58, + AvxVnniInt8=59, + AvxVnniInt8_V512=60, + AvxVnniInt16=61, + AvxVnniInt16_V512=62, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 81532915c78994..fd7d9fc1efec20 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -143,6 +143,12 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X64_GFNI_X64: return ReadyToRunInstructionSet.Gfni; case InstructionSet.X64_GFNI_V256: return ReadyToRunInstructionSet.Gfni_V256; case InstructionSet.X64_GFNI_V512: return ReadyToRunInstructionSet.Gfni_V512; + case InstructionSet.X64_AVXVNNIINT8: return ReadyToRunInstructionSet.AvxVnniInt8; + case InstructionSet.X64_AVXVNNIINT8_X64: return ReadyToRunInstructionSet.AvxVnniInt8; + case InstructionSet.X64_AVXVNNIINT8_V512: return ReadyToRunInstructionSet.AvxVnniInt8_V512; + case InstructionSet.X64_AVXVNNIINT16: return ReadyToRunInstructionSet.AvxVnniInt16; + case InstructionSet.X64_AVXVNNIINT16_X64: return ReadyToRunInstructionSet.AvxVnniInt16; + case InstructionSet.X64_AVXVNNIINT16_V512: return ReadyToRunInstructionSet.AvxVnniInt16_V512; default: throw new Exception("Unknown instruction set"); } @@ -226,6 +232,12 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.X86_GFNI_X64: return null; case InstructionSet.X86_GFNI_V256: return ReadyToRunInstructionSet.Gfni_V256; case InstructionSet.X86_GFNI_V512: return ReadyToRunInstructionSet.Gfni_V512; + case InstructionSet.X86_AVXVNNIINT8: return ReadyToRunInstructionSet.AvxVnniInt8; + case InstructionSet.X86_AVXVNNIINT8_X64: return null; + case InstructionSet.X86_AVXVNNIINT8_V512: return ReadyToRunInstructionSet.AvxVnniInt8_V512; + case InstructionSet.X86_AVXVNNIINT16: return ReadyToRunInstructionSet.AvxVnniInt16; + case InstructionSet.X86_AVXVNNIINT16_X64: return null; + case InstructionSet.X86_AVXVNNIINT16_V512: return ReadyToRunInstructionSet.AvxVnniInt16_V512; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index c245aa94d4a842..37fa95cefab153 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -90,6 +90,10 @@ public enum InstructionSet X64_GFNI = InstructionSet_X64.GFNI, X64_GFNI_V256 = InstructionSet_X64.GFNI_V256, X64_GFNI_V512 = InstructionSet_X64.GFNI_V512, + X64_AVXVNNIINT8 = InstructionSet_X64.AVXVNNIINT8, + X64_AVXVNNIINT8_V512 = InstructionSet_X64.AVXVNNIINT8_V512, + X64_AVXVNNIINT16 = InstructionSet_X64.AVXVNNIINT16, + X64_AVXVNNIINT16_V512 = InstructionSet_X64.AVXVNNIINT16_V512, X64_X86Base_X64 = InstructionSet_X64.X86Base_X64, X64_SSE_X64 = InstructionSet_X64.SSE_X64, X64_SSE2_X64 = InstructionSet_X64.SSE2_X64, @@ -118,6 +122,8 @@ public enum InstructionSet X64_AVX10v2_X64 = InstructionSet_X64.AVX10v2_X64, X64_AVX10v2_V512_X64 = InstructionSet_X64.AVX10v2_V512_X64, X64_GFNI_X64 = InstructionSet_X64.GFNI_X64, + X64_AVXVNNIINT8_X64 = InstructionSet_X64.AVXVNNIINT8_X64, + X64_AVXVNNIINT16_X64 = InstructionSet_X64.AVXVNNIINT16_X64, X86_X86Base = InstructionSet_X86.X86Base, X86_SSE = InstructionSet_X86.SSE, X86_SSE2 = InstructionSet_X86.SSE2, @@ -164,6 +170,10 @@ public enum InstructionSet X86_GFNI = InstructionSet_X86.GFNI, X86_GFNI_V256 = InstructionSet_X86.GFNI_V256, X86_GFNI_V512 = InstructionSet_X86.GFNI_V512, + X86_AVXVNNIINT8 = InstructionSet_X86.AVXVNNIINT8, + X86_AVXVNNIINT8_V512 = InstructionSet_X86.AVXVNNIINT8_V512, + X86_AVXVNNIINT16 = InstructionSet_X86.AVXVNNIINT16, + X86_AVXVNNIINT16_V512 = InstructionSet_X86.AVXVNNIINT16_V512, X86_X86Base_X64 = InstructionSet_X86.X86Base_X64, X86_SSE_X64 = InstructionSet_X86.SSE_X64, X86_SSE2_X64 = InstructionSet_X86.SSE2_X64, @@ -192,6 +202,8 @@ public enum InstructionSet X86_AVX10v2_X64 = InstructionSet_X86.AVX10v2_X64, X86_AVX10v2_V512_X64 = InstructionSet_X86.AVX10v2_V512_X64, X86_GFNI_X64 = InstructionSet_X86.GFNI_X64, + X86_AVXVNNIINT8_X64 = InstructionSet_X86.AVXVNNIINT8_X64, + X86_AVXVNNIINT16_X64 = InstructionSet_X86.AVXVNNIINT16_X64, } public enum InstructionSet_ARM64 { @@ -283,34 +295,40 @@ public enum InstructionSet_X64 GFNI = 44, GFNI_V256 = 45, GFNI_V512 = 46, - X86Base_X64 = 47, - SSE_X64 = 48, - SSE2_X64 = 49, - SSE3_X64 = 50, - SSSE3_X64 = 51, - SSE41_X64 = 52, - SSE42_X64 = 53, - AVX_X64 = 54, - AVX2_X64 = 55, - AES_X64 = 56, - BMI1_X64 = 57, - BMI2_X64 = 58, - FMA_X64 = 59, - LZCNT_X64 = 60, - PCLMULQDQ_X64 = 61, - POPCNT_X64 = 62, - AVXVNNI_X64 = 63, - X86Serialize_X64 = 64, - AVX512F_X64 = 65, - AVX512BW_X64 = 66, - AVX512CD_X64 = 67, - AVX512DQ_X64 = 68, - AVX512VBMI_X64 = 69, - AVX10v1_X64 = 70, - AVX10v1_V512_X64 = 71, - AVX10v2_X64 = 72, - AVX10v2_V512_X64 = 73, - GFNI_X64 = 74, + AVXVNNIINT8 = 47, + AVXVNNIINT8_V512 = 48, + AVXVNNIINT16 = 49, + AVXVNNIINT16_V512 = 50, + X86Base_X64 = 51, + SSE_X64 = 52, + SSE2_X64 = 53, + SSE3_X64 = 54, + SSSE3_X64 = 55, + SSE41_X64 = 56, + SSE42_X64 = 57, + AVX_X64 = 58, + AVX2_X64 = 59, + AES_X64 = 60, + BMI1_X64 = 61, + BMI2_X64 = 62, + FMA_X64 = 63, + LZCNT_X64 = 64, + PCLMULQDQ_X64 = 65, + POPCNT_X64 = 66, + AVXVNNI_X64 = 67, + X86Serialize_X64 = 68, + AVX512F_X64 = 69, + AVX512BW_X64 = 70, + AVX512CD_X64 = 71, + AVX512DQ_X64 = 72, + AVX512VBMI_X64 = 73, + AVX10v1_X64 = 74, + AVX10v1_V512_X64 = 75, + AVX10v2_X64 = 76, + AVX10v2_V512_X64 = 77, + GFNI_X64 = 78, + AVXVNNIINT8_X64 = 79, + AVXVNNIINT16_X64 = 80, } public enum InstructionSet_X86 @@ -363,34 +381,40 @@ public enum InstructionSet_X86 GFNI = 44, GFNI_V256 = 45, GFNI_V512 = 46, - X86Base_X64 = 47, - SSE_X64 = 48, - SSE2_X64 = 49, - SSE3_X64 = 50, - SSSE3_X64 = 51, - SSE41_X64 = 52, - SSE42_X64 = 53, - AVX_X64 = 54, - AVX2_X64 = 55, - AES_X64 = 56, - BMI1_X64 = 57, - BMI2_X64 = 58, - FMA_X64 = 59, - LZCNT_X64 = 60, - PCLMULQDQ_X64 = 61, - POPCNT_X64 = 62, - AVXVNNI_X64 = 63, - X86Serialize_X64 = 64, - AVX512F_X64 = 65, - AVX512BW_X64 = 66, - AVX512CD_X64 = 67, - AVX512DQ_X64 = 68, - AVX512VBMI_X64 = 69, - AVX10v1_X64 = 70, - AVX10v1_V512_X64 = 71, - AVX10v2_X64 = 72, - AVX10v2_V512_X64 = 73, - GFNI_X64 = 74, + AVXVNNIINT8 = 47, + AVXVNNIINT8_V512 = 48, + AVXVNNIINT16 = 49, + AVXVNNIINT16_V512 = 50, + X86Base_X64 = 51, + SSE_X64 = 52, + SSE2_X64 = 53, + SSE3_X64 = 54, + SSSE3_X64 = 55, + SSE41_X64 = 56, + SSE42_X64 = 57, + AVX_X64 = 58, + AVX2_X64 = 59, + AES_X64 = 60, + BMI1_X64 = 61, + BMI2_X64 = 62, + FMA_X64 = 63, + LZCNT_X64 = 64, + PCLMULQDQ_X64 = 65, + POPCNT_X64 = 66, + AVXVNNI_X64 = 67, + X86Serialize_X64 = 68, + AVX512F_X64 = 69, + AVX512BW_X64 = 70, + AVX512CD_X64 = 71, + AVX512DQ_X64 = 72, + AVX512VBMI_X64 = 73, + AVX10v1_X64 = 74, + AVX10v1_V512_X64 = 75, + AVX10v2_X64 = 76, + AVX10v2_V512_X64 = 77, + GFNI_X64 = 78, + AVXVNNIINT8_X64 = 79, + AVXVNNIINT16_X64 = 80, } public unsafe struct InstructionSetFlags : IEnumerable @@ -731,6 +755,14 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X64_GFNI_X64); if (resultflags.HasInstructionSet(InstructionSet.X64_GFNI_X64)) resultflags.AddInstructionSet(InstructionSet.X64_GFNI); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT8)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT8_X64); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT8_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT8); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT16)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT16_X64); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT16_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT16); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) resultflags.AddInstructionSet(InstructionSet.X64_X86Base); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE2)) @@ -845,6 +877,14 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT8); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT16); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT8_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT16_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_Vector128)) resultflags.AddInstructionSet(InstructionSet.X64_SSE); if (resultflags.HasInstructionSet(InstructionSet.X64_Vector256)) @@ -974,6 +1014,14 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2_V512)) resultflags.AddInstructionSet(InstructionSet.X86_AVX10v1_V512); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X86_AVXVNNIINT8); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2)) + resultflags.AddInstructionSet(InstructionSet.X86_AVXVNNIINT16); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVXVNNIINT8_V512); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v2_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVXVNNIINT16_V512); if (resultflags.HasInstructionSet(InstructionSet.X86_Vector128)) resultflags.AddInstructionSet(InstructionSet.X86_SSE); if (resultflags.HasInstructionSet(InstructionSet.X86_Vector256)) @@ -1115,6 +1163,10 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_GFNI_X64)) resultflags.AddInstructionSet(InstructionSet.X64_GFNI); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT8_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT8); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT16_X64)) + resultflags.AddInstructionSet(InstructionSet.X64_AVXVNNIINT16); if (resultflags.HasInstructionSet(InstructionSet.X64_X86Base)) resultflags.AddInstructionSet(InstructionSet.X64_SSE); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) @@ -1229,6 +1281,14 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX10v1_V512)) resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT8)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT16)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT8_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet.X64_AVXVNNIINT16_V512)) + resultflags.AddInstructionSet(InstructionSet.X64_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X64_SSE)) resultflags.AddInstructionSet(InstructionSet.X64_Vector128); if (resultflags.HasInstructionSet(InstructionSet.X64_AVX)) @@ -1358,6 +1418,14 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX10v1_V512)) resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVXVNNIINT8)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVXVNNIINT16)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVXVNNIINT8_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2_V512); + if (resultflags.HasInstructionSet(InstructionSet.X86_AVXVNNIINT16_V512)) + resultflags.AddInstructionSet(InstructionSet.X86_AVX10v2_V512); if (resultflags.HasInstructionSet(InstructionSet.X86_SSE)) resultflags.AddInstructionSet(InstructionSet.X86_Vector128); if (resultflags.HasInstructionSet(InstructionSet.X86_AVX)) @@ -1498,6 +1566,10 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("gfni", "Gfni", InstructionSet.X64_GFNI, true); yield return new InstructionSetInfo("gfni_v256", "Gfni_V256", InstructionSet.X64_GFNI_V256, true); yield return new InstructionSetInfo("gfni_v512", "Gfni_V512", InstructionSet.X64_GFNI_V512, true); + yield return new InstructionSetInfo("avxvnniint8", "AvxVnniInt8", InstructionSet.X64_AVXVNNIINT8, true); + yield return new InstructionSetInfo("avxvnniint8_v512", "AvxVnniInt8_V512", InstructionSet.X64_AVXVNNIINT8_V512, true); + yield return new InstructionSetInfo("avxvnniint16", "AvxVnniInt16", InstructionSet.X64_AVXVNNIINT16, true); + yield return new InstructionSetInfo("avxvnniint16_v512", "AvxVnniInt16_V512", InstructionSet.X64_AVXVNNIINT16_V512, true); break; case TargetArchitecture.X86: @@ -1547,6 +1619,10 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("gfni", "Gfni", InstructionSet.X86_GFNI, true); yield return new InstructionSetInfo("gfni_v256", "Gfni_V256", InstructionSet.X86_GFNI_V256, true); yield return new InstructionSetInfo("gfni_v512", "Gfni_V512", InstructionSet.X86_GFNI_V512, true); + yield return new InstructionSetInfo("avxvnniint8", "AvxVnniInt8", InstructionSet.X86_AVXVNNIINT8, true); + yield return new InstructionSetInfo("avxvnniint8_v512", "AvxVnniInt8_V512", InstructionSet.X86_AVXVNNIINT8_V512, true); + yield return new InstructionSetInfo("avxvnniint16", "AvxVnniInt16", InstructionSet.X86_AVXVNNIINT16, true); + yield return new InstructionSetInfo("avxvnniint16_v512", "AvxVnniInt16_V512", InstructionSet.X86_AVXVNNIINT16_V512, true); break; } } @@ -1637,6 +1713,10 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); if (HasInstructionSet(InstructionSet.X64_GFNI)) AddInstructionSet(InstructionSet.X64_GFNI_X64); + if (HasInstructionSet(InstructionSet.X64_AVXVNNIINT8)) + AddInstructionSet(InstructionSet.X64_AVXVNNIINT8_X64); + if (HasInstructionSet(InstructionSet.X64_AVXVNNIINT16)) + AddInstructionSet(InstructionSet.X64_AVXVNNIINT16_X64); break; case TargetArchitecture.X86: @@ -1693,6 +1773,8 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X64_AVX10v2_X64); AddInstructionSet(InstructionSet.X64_AVX10v2_V512_X64); AddInstructionSet(InstructionSet.X64_GFNI_X64); + AddInstructionSet(InstructionSet.X64_AVXVNNIINT8_X64); + AddInstructionSet(InstructionSet.X64_AVXVNNIINT16_X64); break; case TargetArchitecture.X86: @@ -1724,6 +1806,8 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.X86_AVX10v2_X64); AddInstructionSet(InstructionSet.X86_AVX10v2_V512_X64); AddInstructionSet(InstructionSet.X86_GFNI_X64); + AddInstructionSet(InstructionSet.X86_AVXVNNIINT8_X64); + AddInstructionSet(InstructionSet.X86_AVXVNNIINT16_X64); break; } } @@ -2068,6 +2152,24 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite else { return InstructionSet.X64_GFNI; } + case "AvxVnniInt8": + if (nestedTypeName == "X64") + { return InstructionSet.X64_AVXVNNIINT8_X64; } + else + if (nestedTypeName == "V512") + { return InstructionSet.X64_AVXVNNIINT8_V512; } + else + { return InstructionSet.X64_AVXVNNIINT8; } + + case "AvxVnniInt16": + if (nestedTypeName == "X64") + { return InstructionSet.X64_AVXVNNIINT16_X64; } + else + if (nestedTypeName == "V512") + { return InstructionSet.X64_AVXVNNIINT16_V512; } + else + { return InstructionSet.X64_AVXVNNIINT16; } + } break; @@ -2204,6 +2306,18 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite else { return InstructionSet.X86_GFNI; } + case "AvxVnniInt8": + if (nestedTypeName == "V512") + { return InstructionSet.X86_AVXVNNIINT8_V512; } + else + { return InstructionSet.X86_AVXVNNIINT8; } + + case "AvxVnniInt16": + if (nestedTypeName == "V512") + { return InstructionSet.X86_AVXVNNIINT16_V512; } + else + { return InstructionSet.X86_AVXVNNIINT16; } + } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index 278ce92bf74464..5eb05ebed94039 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -73,6 +73,10 @@ instructionset ,X86 ,Avx10v2_V512 , ,52 ,AVX10v2_V512 instructionset ,X86 ,Gfni , ,53 ,GFNI ,gfni instructionset ,X86 ,Gfni_V256 , ,54 ,GFNI_V256 ,gfni_v256 instructionset ,X86 ,Gfni_V512 , ,55 ,GFNI_V512 ,gfni_v512 +instructionset ,X86 ,AvxVnniInt8 , ,59 ,AVXVNNIINT8 ,avxvnniint8 +instructionset ,X86 ,AvxVnniInt8_V512 , ,60 ,AVXVNNIINT8_V512 ,avxvnniint8_v512 +instructionset ,X86 ,AvxVnniInt16 , ,61 ,AVXVNNIINT16 ,avxvnniint16 +instructionset ,X86 ,AvxVnniInt16_V512 , ,62 ,AVXVNNIINT16_V512 ,avxvnniint16_v512 instructionset64bit,X86 ,X86Base instructionset64bit,X86 ,SSE @@ -102,6 +106,8 @@ instructionset64bit,X86 ,AVX10v1_V512 instructionset64bit,X86 ,AVX10v2 instructionset64bit,X86 ,AVX10v2_V512 instructionset64bit,X86 ,GFNI +instructionset64bit,X86 ,AVXVNNIINT8 +instructionset64bit,X86 ,AVXVNNIINT16 vectorinstructionset,X86 ,Vector128 vectorinstructionset,X86 ,Vector256 @@ -179,6 +185,10 @@ implication ,X86 ,AVX10v1_V512 ,AVX512VBMI implication ,X86 ,AVX10v1_V512 ,AVX512VBMI_VL implication ,X86 ,AVX10v2 ,AVX10v1 implication ,X86 ,AVX10v2_V512 ,AVX10v1_V512 +implication ,X86 ,AVX10v2 ,AVXVNNIINT8 +implication ,X86 ,AVX10v2 ,AVXVNNIINT16 +implication ,X86 ,AVX10v2_V512 ,AVXVNNIINT8_V512 +implication ,X86 ,AVX10v2_V512 ,AVXVNNIINT16_V512 ; These synthetic ISAs need to appear after the core ISAs ; as they depend on the other implications being correct first diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 0be5ceff63d423..652e4e3e75c4cc 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1435,6 +1435,24 @@ void EEJitManager::SetCpuInfo() } } + if ((cpuFeatures & XArchIntrinsicConstants_AvxVnniInt8) != 0) + { + if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVXVNNIINT8)) + { + CPUCompileFlags.Set(InstructionSet_AVXVNNIINT8); + CPUCompileFlags.Set(InstructionSet_AVXVNNIINT8_V512); + } + } + + if ((cpuFeatures & XArchIntrinsicConstants_AvxVnniInt16) != 0) + { + if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVXVNNIINT16)) + { + CPUCompileFlags.Set(InstructionSet_AVXVNNIINT16); + CPUCompileFlags.Set(InstructionSet_AVXVNNIINT16_V512); + } + } + if ((cpuFeatures & XArchIntrinsicConstants_Avx10v2) != 0) { if (CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableAVX10v2)) diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index 7a233b31eda84d..993b3b3512e4c8 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -331,6 +331,16 @@ int minipal_getcpufeatures(void) result |= XArchIntrinsicConstants_AvxVnni; } + if ((cpuidInfo[CPUID_EDX] & (1 << 4)) != 0) // AVX-VNNI-INT8 + { + result |= XArchIntrinsicConstants_AvxVnniInt8; + } + + if ((cpuidInfo[CPUID_EDX] & (1 << 10)) != 0) // AVX-VNNI-INT16 + { + result |= XArchIntrinsicConstants_AvxVnniInt16; + } + if (IsApxEnabled() && apxStateSupport()) { if ((cpuidInfo[CPUID_EDX] & (1 << 21)) != 0) // Apx @@ -353,6 +363,8 @@ int minipal_getcpufeatures(void) if (avx10Version >= 2) // Avx10.2 { result |= XArchIntrinsicConstants_Avx10v2; + result |= XArchIntrinsicConstants_AvxVnniInt8; // AvxVnniInt8 + result |= XArchIntrinsicConstants_AvxVnniInt16; // AvxVnniInt16 } // We assume that the Avx10/V512 support can be inferred from diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index b88043d4cdb92a..b591d6cc51a917 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -35,6 +35,8 @@ enum XArchIntrinsicConstants XArchIntrinsicConstants_Vpclmulqdq = 0x200000, XArchIntrinsicConstants_Avx10v2 = 0x400000, XArchIntrinsicConstants_Gfni = 0x800000, + XArchIntrinsicConstants_AvxVnniInt8 = 0x01000000, + XArchIntrinsicConstants_AvxVnniInt16 = 0x02000000, }; #endif // HOST_X86 || HOST_AMD64