Fix: #20 issue - misrouted write completion

WCH FIFO in slv_switch_wr now stores AWID & misrouted flag. The FIFO
content is used to feed OoO module for write response coompletion.
This changes will prevent to complete a misrouted transaction while
the write data channel is still transmitting data.

Change: Synthesis flow update

Slight updates to extract logic usage and estimates NAND2 gate count

Author: dpretet

rtl/axicb_slv_ooo.sv

@@ -155,8 +155,6 @@ module axicb_slv_ooo
 
         // Back pressure to address channel, block any further transaction
         // as soon an ID FIFO is full.
-        // TODO: could be optimized but the loop back to the initiatior
-        //       from the FIFO could be unavoidable.
         always_comb a_full = |id_full;
 
     end

rtl/axicb_slv_switch_rd.sv

@@ -221,8 +221,8 @@ module axicb_slv_switch_rd
 
     assign c_end = i_rvalid & i_rready & i_rlast;
 
-    // Follow-up rcompletion len for mis-routed traffic
-    // which need to be recreated
+    // Follow-up completion len for misrouted traffic
+    // to create RLAST flag
     always @ (posedge aclk or negedge aresetn) begin
         if (!aresetn) begin
             rlen <= 8'h0;

rtl/axicb_slv_switch_wr.sv

@@ -91,6 +91,9 @@ module axicb_slv_switch_wr
     logic                  bch_full;
     logic                  wch_empty;
 
+    logic [AXI_ID_W  -1:0] a_id;
+    logic                  a_mr;
+
     logic                  bch_en;
     logic                  bch_en_c;
     logic                  bch_en_r;
@@ -161,7 +164,7 @@ module axicb_slv_switch_wr
                                               aw_misrouting;
 
     assign o_awch = i_awch;
-    
+
     assign aw_misrouting_c = slv_aw_targeted=='0;
 
     // Create a fake ready handshake in case a master agent targets a
@@ -192,18 +195,18 @@ module axicb_slv_switch_wr
     #(
         .PASS_THRU  (0),
         .ADDR_WIDTH (8),
-        .DATA_WIDTH (SLV_NB)
+        .DATA_WIDTH (1 + SLV_NB + AXI_ID_W)
     )
     wch_gnt_fifo
     (
         .aclk     (aclk),
         .aresetn  (aresetn),
         .srst     (srst),
         .flush    (1'b0),
-        .data_in  (slv_aw_targeted),
+        .data_in  ({aw_misrouting_c, slv_aw_targeted, i_awch[AXI_ADDR_W+:AXI_ID_W]}),
         .push     (i_awvalid & i_awready),
         .full     (wch_full),
-        .data_out (slv_w_targeted),
+        .data_out ({a_mr, slv_w_targeted, a_id}),
         .pull     (i_wvalid & i_wready & i_wlast),
         .empty    (wch_empty)
     );
@@ -234,7 +237,7 @@ module axicb_slv_switch_wr
     ///////////////////////////////////////////////////////////////////////////
 
     // OoO ID Management
-    axicb_slv_ooo 
+    axicb_slv_ooo
     #(
         .RD_PATH         (0),
         .AXI_ID_W        (AXI_ID_W),
@@ -243,18 +246,18 @@ module axicb_slv_switch_wr
         .MST_ID_MASK     (MST_ID_MASK),
         .CCH_W           (BCH_W)
     )
-    bresp_ooo 
+    bresp_ooo
     (
         .aclk    (aclk),
         .aresetn (aresetn),
         .srst    (srst),
-        .a_valid (i_awvalid),
-        .a_ready (i_awready),
+        .a_valid (i_wvalid & i_wlast & !wch_empty),
+        .a_ready (i_wready),
         .a_full  (bch_full),
-        .a_id    (i_awch[AXI_ADDR_W+:AXI_ID_W]),
+        .a_id    (a_id),
         .a_len   ('0),
-        .a_ix    (slv_aw_targeted),
-        .a_mr    (aw_misrouting_c),
+        .a_ix    (slv_w_targeted),
+        .a_mr    (a_mr),
         .c_en    (bch_en),
         .c_grant (bch_grant),
         .c_mr    (bch_mr),
@@ -283,7 +286,7 @@ module axicb_slv_switch_wr
         end
     end
 
-    // TODO: is it really usefull ? round-robin should pass anyway a 
+    // TODO: is it really usefull ? round-robin should pass anyway a
     // grant value if unmasked value > 0
     assign bch_en = bch_en_c | bch_en_r;
 

syn/yosys/area.md

@@ -0,0 +1,19 @@
+# Synthesis with cmos.lib
+
+DFF: 10 NAND2
+DFFSR: 16 NAND2
+NOR: 3 NAND2
+NOT: 1 NAND2
+NAND: 1 NAND2
+
+AXI4 Crossbar:
+
+  Name                          Count       NAND2 Count
+  ------------------------------------------------------
+  DFF                           10656       106560
+  DFFSR                          2928       46848
+  NAND                          67013       67013
+  NOR                           23796       71388
+  NOT                            9831       9831
+
+  Total                        228448       301640

syn/yosys/axicb_axi4.ys

@@ -39,3 +39,6 @@ clean
 
 # write synthesized design
 write_verilog axicb_crossbar_top.v
+
+# drop usage report
+stat -liberty cmos.lib

syn/yosys/axicb_axi4lite.ys

@@ -40,3 +40,6 @@ clean
 
 # write synthesized design
 write_verilog axicb_crossbar_lite_top.v
+
+# drop usage report
+stat -liberty cmos.lib

syn/yosys/cmos.lib

@@ -1,5 +1,3 @@
-// test comment
-/* test comment */
 library(demo) {
   cell(BUF) {
     area: 6;

syn/yosys/constraints.sdc

@@ -0,0 +1,2 @@
+create_clock -name aclk -period 100 [get_ports aclk]
+

syn/yosys/syn_asic.sh

@@ -15,6 +15,6 @@ fi
 echo "INFO: Start synthesis flow"
 yosys -V
 
-yosys "$design"
+yosys "$design" > "$design.log"
 
 exit 0