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Fix: correct AXI4 signals and paths along the AXI fabric
1 parent 804846e commit 3bca727

11 files changed

+599
-272
lines changed

‎rtl/friscv_cache_block_fetcher.sv‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -165,14 +165,17 @@ module friscv_cache_block_fetcher
165165
// later in cache miss
166166
always @ (posedge aclk or negedge aresetn) begin
167167
if (!aresetn) begin
168-
araddr_ffd <= {AXI_ADDR_W{1'b0}};
169-
arid_ffd <= {AXI_ID_W{1'b0}};
168+
araddr_ffd <= '0;
169+
arid_ffd <= '0;
170+
arprot_ffd <= '0;
170171
end else if (srst) begin
171-
araddr_ffd <= {AXI_ADDR_W{1'b0}};
172-
arid_ffd <= {AXI_ID_W{1'b0}};
172+
araddr_ffd <= '0;
173+
arid_ffd <= '0;
174+
arprot_ffd <= '0;
173175
end else begin
174176
araddr_ffd <= cache_raddr;
175177
arid_ffd <= cache_rid;
178+
arprot_ffd <= cache_rprot;
176179
end
177180
end
178181

@@ -181,7 +184,6 @@ module friscv_cache_block_fetcher
181184

182185
// Cache read interface
183186
assign cache_ren = arvalid & arready | sel_mf | (flush & arvalid);
184-
// assign cache_ren = arvalid & arready | (loader != IDLE && (!(flush & !arvalid) || !(rac_empty & !arvalid)));
185187
assign cache_raddr = sel_mf ? araddr_ffd : araddr;
186188
assign cache_rid = sel_mf ? arid_ffd : arid;
187189
assign cache_rprot = sel_mf ? arprot_ffd : arprot;

‎rtl/friscv_memfy.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@ module friscv_memfy
123123
output logic arlock,
124124
input wire rvalid,
125125
output logic rready,
126-
input wire rlast,
127126
input wire [AXI_ID_W -1:0] rid,
128127
input wire [2 -1:0] rresp,
129128
input wire [AXI_DATA_W -1:0] rdata

‎rtl/friscv_processing.sv‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,6 @@ module friscv_processing
9999
output logic arlock,
100100
input wire rvalid,
101101
output logic rready,
102-
input wire rlast,
103102
input wire [AXI_ID_W -1:0] rid,
104103
input wire [2 -1:0] rresp,
105104
input wire [AXI_DATA_W -1:0] rdata
@@ -381,7 +380,6 @@ module friscv_processing
381380
.arlock (arlock),
382381
.rvalid (rvalid),
383382
.rready (rready),
384-
.rlast (rlast),
385383
.rid (rid),
386384
.rresp (rresp),
387385
.rdata (rdata)

‎rtl/friscv_rv32i_core.sv‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,6 @@ module friscv_rv32i_core
278278
logic memfy_arlock;
279279
logic memfy_rvalid;
280280
logic memfy_rready;
281-
logic memfy_rlast;
282281
logic [AXI_ID_W -1:0] memfy_rid;
283282
logic [2 -1:0] memfy_rresp;
284283
logic [XLEN -1:0] memfy_rdata;
@@ -764,7 +763,6 @@ module friscv_rv32i_core
764763
.arlock (memfy_arlock),
765764
.rvalid (memfy_rvalid),
766765
.rready (memfy_rready),
767-
.rlast (memfy_rlast),
768766
.rid (memfy_rid),
769767
.rresp (memfy_rresp),
770768
.rdata (memfy_rdata)
@@ -899,7 +897,6 @@ module friscv_rv32i_core
899897

900898
assign memfy_rvalid = dmem_rvalid;
901899
assign dmem_rready = memfy_rready;
902-
assign memfy_rlast = dmem_rlast;
903900
assign memfy_rid = dmem_rid;
904901
assign memfy_rresp = dmem_rresp;
905902
assign memfy_rdata = dmem_rdata;

‎rtl/friscv_rv32i_platform.sv‎

Lines changed: 53 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -469,6 +469,7 @@ module friscv_rv32i_platform
469469
.dmem_awlock (dmem_awlock),
470470
.dmem_wvalid (dmem_wvalid),
471471
.dmem_wready (dmem_wready),
472+
.dmem_wlast (dmem_wlast),
472473
.dmem_wdata (dmem_wdata),
473474
.dmem_wstrb (dmem_wstrb),
474475
.dmem_bvalid (dmem_bvalid),
@@ -501,6 +502,7 @@ module friscv_rv32i_platform
501502
.SLV_NB (SLV_NB),
502503
.MST_PIPELINE (MST_PIPELINE),
503504
.SLV_PIPELINE (SLV_PIPELINE),
505+
.AXI_SIGNALING (AXI_SIGNALING),
504506
.USER_SUPPORT (USER_SUPPORT),
505507
.AXI_AUSER_W (AXI_AUSER_W),
506508
.AXI_WUSER_W (AXI_WUSER_W),
@@ -611,22 +613,22 @@ module friscv_rv32i_platform
611613
.slv1_awvalid (dmem_awvalid),
612614
.slv1_awready (dmem_awready),
613615
.slv1_awaddr (dmem_awaddr),
614-
.slv1_awlen (dmem_arlen),
616+
.slv1_awlen (dmem_awlen),
615617
.slv1_awsize ('0),
616-
.slv1_awburst (dmem_arburst),
617-
.slv1_awlock (dmem_arlock),
618+
.slv1_awburst (dmem_awburst),
619+
.slv1_awlock (dmem_awlock),
618620
.slv1_awcache ('0),
619-
.slv1_awprot (imem_arprot),
621+
.slv1_awprot (dmem_awprot),
620622
.slv1_awqos ('0),
621623
.slv1_awregion ('0),
622-
.slv1_awid (dmem_arid),
624+
.slv1_awid (dmem_awid),
623625
.slv1_awuser ('0),
624626
.slv1_wvalid (dmem_wvalid),
625627
.slv1_wready (dmem_wready),
626628
.slv1_wlast (dmem_wlast),
627629
.slv1_wdata (dmem_wdata),
628630
.slv1_wstrb (dmem_wstrb),
629-
.slv1_wuser (1'b0),
631+
.slv1_wuser ('0),
630632
.slv1_bvalid (dmem_bvalid),
631633
.slv1_bready (dmem_bready),
632634
.slv1_bid (dmem_bid),
@@ -643,7 +645,7 @@ module friscv_rv32i_platform
643645
.slv1_arprot (dmem_arprot),
644646
.slv1_arqos ('0),
645647
.slv1_arregion ('0),
646-
.slv1_arid (imem_arid),
648+
.slv1_arid (dmem_arid),
647649
.slv1_aruser ('0),
648650
.slv1_rvalid (dmem_rvalid),
649651
.slv1_rready (dmem_rready),
@@ -652,9 +654,9 @@ module friscv_rv32i_platform
652654
.slv1_rresp (dmem_rresp),
653655
.slv1_rdata (dmem_rdata),
654656
.slv1_ruser (),
655-
.slv2_aclk (1'h0),
656-
.slv2_aresetn (1'h0),
657-
.slv2_srst (1'h0),
657+
.slv2_aclk ('0),
658+
.slv2_aresetn ('0),
659+
.slv2_srst ('0),
658660
.slv2_awvalid ('0),
659661
.slv2_awready (),
660662
.slv2_awaddr ('0),
@@ -693,15 +695,15 @@ module friscv_rv32i_platform
693695
.slv2_arid ('0),
694696
.slv2_aruser ('0),
695697
.slv2_rvalid (),
696-
.slv2_rready (1'h1),
698+
.slv2_rready ('1),
697699
.slv2_rlast (),
698700
.slv2_rid (),
699701
.slv2_rresp (),
700702
.slv2_rdata (),
701703
.slv2_ruser (),
702-
.slv3_aclk (1'h0),
703-
.slv3_aresetn (1'h0),
704-
.slv3_srst (1'h0),
704+
.slv3_aclk ('0),
705+
.slv3_aresetn ('0),
706+
.slv3_srst ('0),
705707
.slv3_awvalid ('0),
706708
.slv3_awready (),
707709
.slv3_awaddr ('0),
@@ -740,7 +742,7 @@ module friscv_rv32i_platform
740742
.slv3_arid ('0),
741743
.slv3_aruser ('0),
742744
.slv3_rvalid (),
743-
.slv3_rready (1'h1),
745+
.slv3_rready ('1),
744746
.slv3_rlast (),
745747
.slv3_rid (),
746748
.slv3_rresp (),
@@ -772,7 +774,7 @@ module friscv_rv32i_platform
772774
.mst0_bready (mem_bready),
773775
.mst0_bid (mem_bid),
774776
.mst0_bresp (mem_bresp),
775-
.mst0_buser (1'b0),
777+
.mst0_buser ('0),
776778
.mst0_arvalid (mem_arvalid),
777779
.mst0_arready (mem_arready),
778780
.mst0_araddr (mem_araddr),
@@ -792,7 +794,7 @@ module friscv_rv32i_platform
792794
.mst0_rid (mem_rid),
793795
.mst0_rresp (mem_rresp),
794796
.mst0_rdata (mem_rdata),
795-
.mst0_ruser (1'b0),
797+
.mst0_ruser ('0),
796798
.mst1_aclk (aclk),
797799
.mst1_aresetn (aresetn),
798800
.mst1_srst (srst),
@@ -819,7 +821,7 @@ module friscv_rv32i_platform
819821
.mst1_bready (ios_bready),
820822
.mst1_bid (ios_bid),
821823
.mst1_bresp (ios_bresp),
822-
.mst1_buser (1'b0),
824+
.mst1_buser ('0),
823825
.mst1_arvalid (ios_arvalid),
824826
.mst1_arready (ios_arready),
825827
.mst1_araddr (ios_araddr),
@@ -839,12 +841,12 @@ module friscv_rv32i_platform
839841
.mst1_rid (ios_rid),
840842
.mst1_rresp (ios_rresp),
841843
.mst1_rdata (ios_rdata),
842-
.mst1_ruser (1'b0),
843-
.mst2_aclk (1'h0),
844-
.mst2_aresetn (1'h0),
845-
.mst2_srst (1'h0),
844+
.mst1_ruser ('0),
845+
.mst2_aclk ('0),
846+
.mst2_aresetn ('0),
847+
.mst2_srst ('0),
846848
.mst2_awvalid (),
847-
.mst2_awready (1'h1),
849+
.mst2_awready ('1),
848850
.mst2_awlen (),
849851
.mst2_awsize (),
850852
.mst2_awburst (),
@@ -856,18 +858,18 @@ module friscv_rv32i_platform
856858
.mst2_awid (),
857859
.mst2_awuser (),
858860
.mst2_wvalid (),
859-
.mst2_wready (1'h1),
861+
.mst2_wready ('1),
860862
.mst2_wlast (),
861863
.mst2_wdata (),
862864
.mst2_wstrb (),
863865
.mst2_wuser (),
864-
.mst2_bvalid (1'h0),
866+
.mst2_bvalid ('0),
865867
.mst2_bready (),
866-
.mst2_bid ({AXI_ID_W{1'b0}}),
867-
.mst2_bresp (2'h0),
868-
.mst2_buser (1'h0),
868+
.mst2_bid ('0),
869+
.mst2_bresp ('0),
870+
.mst2_buser ('0),
869871
.mst2_arvalid (),
870-
.mst2_arready (1'b1),
872+
.mst2_arready ('1),
871873
.mst2_arlen (),
872874
.mst2_arsize (),
873875
.mst2_arburst (),
@@ -878,18 +880,18 @@ module friscv_rv32i_platform
878880
.mst2_arregion (),
879881
.mst2_arid (),
880882
.mst2_aruser (),
881-
.mst2_rvalid (1'h0),
883+
.mst2_rvalid ('0),
882884
.mst2_rready (),
883-
.mst2_rlast (1'h0),
884-
.mst2_rid ({AXI_ID_W{1'b0}}),
885-
.mst2_rresp (2'h0),
886-
.mst2_rdata ({AXI_DATA_W{1'b0}}),
887-
.mst2_ruser (1'b0),
888-
.mst3_aclk (1'h0),
889-
.mst3_aresetn (1'h0),
890-
.mst3_srst (1'h0),
885+
.mst2_rlast ('0),
886+
.mst2_rid ('0),
887+
.mst2_rresp ('0),
888+
.mst2_rdata ('0),
889+
.mst2_ruser ('0),
890+
.mst3_aclk ('0),
891+
.mst3_aresetn ('0),
892+
.mst3_srst ('0),
891893
.mst3_awvalid (),
892-
.mst3_awready (1'h1),
894+
.mst3_awready ('1),
893895
.mst3_awlen (),
894896
.mst3_awsize (),
895897
.mst3_awburst (),
@@ -901,18 +903,18 @@ module friscv_rv32i_platform
901903
.mst3_awid (),
902904
.mst3_awuser (),
903905
.mst3_wvalid (),
904-
.mst3_wready (1'h1),
906+
.mst3_wready ('1),
905907
.mst3_wlast (),
906908
.mst3_wdata (),
907909
.mst3_wstrb (),
908910
.mst3_wuser (),
909-
.mst3_bvalid (1'h0),
911+
.mst3_bvalid ('0),
910912
.mst3_bready (),
911-
.mst3_bid ({AXI_ID_W{1'b0}}),
912-
.mst3_bresp (2'h0),
913-
.mst3_buser (1'h0),
913+
.mst3_bid ('0),
914+
.mst3_bresp ('0),
915+
.mst3_buser ('0),
914916
.mst3_arvalid (),
915-
.mst3_arready (1'b1),
917+
.mst3_arready ('1),
916918
.mst3_arlen (),
917919
.mst3_arsize (),
918920
.mst3_arburst (),
@@ -923,13 +925,13 @@ module friscv_rv32i_platform
923925
.mst3_arregion (),
924926
.mst3_arid (),
925927
.mst3_aruser (),
926-
.mst3_rvalid (1'h0),
928+
.mst3_rvalid ('0),
927929
.mst3_rready (),
928-
.mst3_rlast (1'h0),
929-
.mst3_rid ({AXI_ID_W{1'b0}}),
930-
.mst3_rresp (2'h0),
931-
.mst3_rdata ({AXI_DATA_W{1'b0}}),
932-
.mst3_ruser (1'b0)
930+
.mst3_rlast ('0),
931+
.mst3_rid ('0),
932+
.mst3_rresp ('0),
933+
.mst3_rdata ('0),
934+
.mst3_ruser ('0)
933935
);
934936

935937
friscv_io_subsystem

‎test/common/debug_core_icarus.gtkw‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
33
[*] Sun Oct 2 11:44:15 2022
44
[*]
5-
[dumpfile] "/Users/damien/workspace/hdl/friscv/test/wba_testsuite/friscv_testbench.vcd"
5+
[dumpfile] "/Users/damien/workspace/hdl/friscv/test/riscv-tests/friscv_testbench.fst"
66
[dumpfile_mtime] "Sun Oct 2 11:44:07 2022"
77
[dumpfile_size] 3143671
88
[savefile] "/Users/damien/workspace/hdl/friscv/test/common/debug_core_icarus.gtkw"

‎test/common/debug_core_verilator.gtkw‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
33
[*] Sat Sep 16 11:53:18 2023
44
[*]
5-
[dumpfile] "/Users/damien/workspace/hdl/friscv/test/riscv-tests/friscv_testbench.vcd"
5+
[dumpfile] "/Users/damien/workspace/hdl/friscv/test/riscv-tests/friscv_testbench.fst"
66
[dumpfile_mtime] "Wed Sep 13 18:20:19 2023"
77
[dumpfile_size] 1779051
88
[savefile] "/Users/damien/workspace/hdl/friscv/test/common/debug_core_verilator.gtkw"

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