Sigrok, pulseview as desktop client

[zigastegu]

Hello,
thank you for your work.
Do you know about https://sigrok.org/ ? It is great and in active development.

[drandyhaas]

Hi. Yes, I'm aware of it. I looked a bit at what would need to be done to add support for this board, and it didn't look easy. I couldn't really even figure out where to start. I think some sigrok expert would have to do it.

[zigastegu]

Does your board/fpga have a posibility to send data over usb?
I could try to write a device driver as there are already boards supported with uart interface.

[drandyhaas]

Yes, it sends data over usb with a uart protocol.
See this file for a minimal example in python of how to setup and then get data from the board:
https://github.com/drandyhaas/Haasoscope/blob/master/software/serial_read.py
Once the board is set up, you get events by sending (over uart) two bytes: 100 10.

[zigastegu]

Does fpga have native usb protocol? Uart is probably not fast enough for highest bitrates.

[drandyhaas]

The basic uart is just 1.5 Mbps, which is ~10 Hz of events (depending on num samples per event).
But there is also a USB2 "hat" available that plugs on the board and enables higher speed uart readout at about 30 Mbps (20x faster), which gets you ~hundreds of Hz!
See the guide: https://docs.google.com/document/d/1euyzCGzQo0u9APwEeior9fpyhcYWbkNxYQaV7SuFfoE/edit?usp=sharing
and look for "USB2".

[zigastegu]

Any chance you would lend me one of this uart oscilloscopes? Would like to try and add support in sigrok project. I already have "USB hat".

[drandyhaas]

Sure! I'll put the latest firmware on it, which also has the logic analyzer functionality.
Just send me your address.

[zigastegu]

Ok, I got around setting oscilloscope. Had some hiccups when other FTDI serial only adapters were also recognized as USB2. :)

looking at PC <-> Haasoscope serial communication

[drandyhaas]

Any progress?

[zigastegu]

What would be the procedure to get only logic analyzer data?

0. initialization as in serial_read.py (this seems to initialize more than just logic analyzer part)
1. enable logic part ('145 5') so 5th (virtual channel) on top of all analog channels
2. receive data

[drandyhaas]

I don't think there's a way to get only the logic analyzer data with the current firmware.

[zigastegu]

Ok, I see. Not a problem.
Fooling around: https://youtu.be/BYRskn1hWNk
Board is still capturing 4 adc and logic, sw thinks it is only 4 adc :)

[zigastegu]

I can see that drawing matplots considerably limits communication refresh rate. Probably should be done in separate Thread (https://www.tutorialspoint.com/python/python_multithreading.htm).
Now that I have smaller working version, will try to add it to sigrok

[zigastegu]

Hi Andy, I am in the process of writing HaasoscopeLib.py alternative. I will do that before sigrok implementation, to I understand the project a bit better.
Is that ok with you?
Progress will be visible on my fork. Because I am on version v8.81 of hw, will ask you to check some things.

IOExpanders work and all layers in between (i2c, protocol, uart). In test I can already turn on/off some leds

[drandyhaas]

Ok, if you like. Just let me know when you want me to have a look.