KiCadRoutingTools — what's new (June 2026)

[drandyhaas]

Since the March–May update the big themes are one-click distribution and a set of new ways to steer the router. Highlights below; full history in git log.

Distribution & install — now a Plugin & Content Manager plugin

• Install straight from KiCad's PCM. The project is packaged as a PCM plugin (metadata.json, v0.15.4+). Prebuilt Rust router binaries ship via GitHub Releases for Linux x86_64, macOS arm64 + x86_64, and Windows x86_64, bundled into a single cross-platform PCM zip; a small startup resolver picks the right binary for your machine. No local Rust build required.
• First-launch dependency check reads requirements.txt as the source of truth (scipy, shapely — KiCad already bundles numpy/wxPython) and offers a one-click pip install. Fixed a deps-install hang on PCM-installed copies.
• Windows OneDrive: the source installer now follows Documents when it's redirected into OneDrive.
• No more shadowing. If you also install from source, the installer detects a conflicting PCM copy of this plugin (which would otherwise sit next to the local install on sys.path and cause stale-code errors like batch_route() got an unexpected keyword argument) and moves it aside; --keep-pcm opts out. Also fixed a symlink-overwrite error on --symlink dev installs.
• Release pipeline documented in docs/release-pipeline.md (tag → CI builds all four platform binaries → PCM submission), including the gotchas and a smoke-test step.

Telling the router where to go — and where not to

New ways to steer routing, both by drawing on a User layer and by honoring native KiCad keepouts:

• Guide corridor (Draw preferred route #7) — draw a polyline on a User layer (default User.1) and the selected nets are routed to follow it as waypoints — source → along your path → target — getting as close as obstacles allow. It's strictly best-effort: a waypoint it can't follow is dropped, so a guide never makes a route fail or adds needless vias, and multiple nets following the same corridor pack alongside one another without overlapping. Endpoints/MST topology are untouched. CLI --guide-corridor; "Follow User-layer guide path" checkbox.
• User-drawn keepout zones (Draw preferred keepout area for routing #27) — draw one or more closed polygons (or rectangles) on a User layer (default User.2) and routed tracks and vias stay out of those areas, on every copper layer — a hard keepout. It applies across single-ended, multipoint, and differential-pair routing, plus plane via-stitching and plane repair. Useful for analog regions, antenna clearances, or mechanical exclusions. CLI --keepout (route.py / route_diff.py); "Keep out of User-layer polygon(s)" checkbox.
• Native KiCad keep-out rule areas (Respect KiCad keep-out rule areas in the routing obstacle map #25) — separate from the User-layer drawing above: the router now also respects KiCad's own (zone … (keepout …)) rule areas — the ones you create with KiCad's keepout/rule-area tool on copper layers, not a User-layer sketch. It blocks only the disallowed item (tracks and/or vias) on the keepout's listed layers, with copper-edge clearance, and is automatic whenever the board has one (no flag), across every routing type. Thanks to @bergmorten.
• Clear after routing — optional "Clear guide layer / Clear keepout layer after routing" checkboxes (off by default) wipe the drawn guide/keepout graphics from their User layer once a route succeeds, so you can draw the next set.

Route by selection (#6)

• Select a set of nets in the KiCad canvas, open the plugin, and those nets (and only those) are pre-selected for routing this run.

Planes

• --skip-existing-zones flag for route_planes (PR Add --skip-existing-zones flag to route_planes #26, @bergmorten): preserve an existing same-net/same-layer zone and only add stitching vias, instead of recreating it.

Under the hood

• Unified the polygon rasterization used by board cutouts and both keepout types into one vectorized geometry kernel — internal cleanup, provably behavior-identical.
• New self-contained, pass/fail test suites with their own bundled boards: guide corridor, user-drawn keepout, and native KiCad rule-area keepout.

Versions

• Same scheme as before: VERSION mirrors the Rust crate's major.minor, and the patch is bumped for Python-only changes.
• Currently at 0.15.7.

Router tuning, honest reporting & speed (mid-June, through b207590)

• Grid-independent (mm-based) cost knobs. The routing cost weights (via, turn, proximity) are now expressed in millimeters and are independent of --grid-step, so the same knobs behave consistently across grid resolutions (Make routing cost knobs mm-based, independent of grid step #69).
• Power-route neck-down. Failed power-tap edges are retried at the default track width with a neck-down near the pad, and neck-down is now available for all single-ended routes with GUI options (default 2.5 mm) (Retry failed power-net tap edges at default track width (neck-down) #72 / Neck-down: retry failed wide power routes at default width (fixes #72) #73).
• More honest completion reporting. Multipoint nets that leave a tap pad unconnected are now counted as failed (Count multipoint nets with unconnected tap pads as failed #71) instead of silently passing.
• Faster obstacle maps. Blocking analysis is vectorized with packed-int64 cell keys, and the obstacle cache replaces np.unique(axis=0) row dedupe with a bitmap dedupe — large speedups on base-map builds (adaptive-grid investigation, Don't print a Claude run's error twice in the transcript #67 / Eliminate Python-side routing bottlenecks: bitmap dedupe + vectorized blocking analysis #68; builds also batched, Rust router: use rayon for parallelism #35 / Batch obstacle-map rasterization: 6.4x faster base map builds #61).
• Docs updated for the mm-calibrated costs, the neck-down options, and a documented known DRC issue.

[drandyhaas]

Update — June 9

Since this post went up: v0.15.7 was released (the PCM packaging described above), and a deep pass on differential-pair routing for boards without fanout stubs — driven by a simple 2-layer LVDS converter board where the diff pairs land directly on SOIC pins and 0805 termination resistors. That path exercised assumptions the BGA-fanout flow never hit, and shook out a chain of fixes:

Diff pairs on bare pads

• Suffix-aware pair matching. Nets now only pair within the same naming convention: /CLK+ pairs with /CLK-, never with an unrelated single-ended /CLK_N that happens to share the base name. Previously whichever negative-suffix net was iterated last silently won the pairing, and the GUI could offer a corrupted pair (P=/CLK+, N=/CLK_N) that couldn't route.
• Bare-pad endpoints. Pairs terminating on bare SMD pads had no stub to derive an escape direction from, so the centerline started/ended on top of the pads — and since the pair's own pads aren't obstacles, the offset P track could run straight across the N pad (shorts, mask bridges). The router now synthesizes an escape direction from the pad geometry (perpendicular to the pad axis, away from the component body) and blocks the pair's own pads outside capsule-shaped pad-entry corridors.
• Polarity swaps are now consistent everywhere. The pad-net swap is applied to the in-memory state too, not just the output — fixing a bug where the post-route cleanup collapsed sub-1mm connectors ending on a swapped pad, leaving visible gaps between tracks and pads.
• Plugin mode applies swaps to the live board. Routing from the GUI added tracks and vias but silently dropped polarity pad swaps, target swaps, and stub layer modifications (the CLI file-writer applied them all). A new board_swaps.py mirrors the file-writer on the open pcbnew board, for both the differential and single-ended tabs.
• Polarity mismatch without pad swaps. With polarity fixing disabled, the router no longer writes crossing connectors that short the pair. It re-routes with the connectors taken out the opposite side at one end (flipping one end flips its P/N handedness — possible for bare-pad endpoints), giving the wrapped route a full-loop turn budget and validating the result for P/N crossings. If no clean flip exists, the pair is skipped with a warning — crossing tracks are never written. The GUI's "Fix polarity swaps" checkbox now defaults to off, since pad-net swaps change the board without touching the schematic; the CLI default is unchanged.

Other fixes since v0.15.7

• Multi-point nets terminating at pads no longer report false routing success when only part of the net was connected.
• Basic-tab UI: fixed a parameter-entry deadlock (entering track width below pcb design rule constraint results in a UI deadlock #30) and the 2-decimal input limit (numerical Parameters in the Basic windows are limited to two decimal places #31).
• New focused diff-pair correctness regression test (tests/test_diff_pair_route.py): routes individual pairs and asserts fully-connected + DRC-clean.
• A guide-corridor extension for differential pairs (Draw preferred route #7) was prototyped and reverted — it needs more work before it's reliable.

Docs: the differential-pair internals writeup (docs/differential-pairs.md) now covers bare-pad endpoint handling, the pairing rules, and the polarity-swap/opposite-side behavior in detail.

[drandyhaas]

Update — June 9 (later): multi-point differential pairs

Continuing the bare-pad diff-pair work from the previous update, the router can now handle multi-point differential pairs — pairs whose nets land on 3+ pad-pair terminals (e.g. connector → termination resistor → IC pins), which previously left everything beyond the closest two terminals unrouted.

Multi-point diff pairs route as a chain

A diff pair can't tap onto the middle of an existing pair of tracks — the tapping leg's P/N would have to cross the existing pair. And each pad-pair terminal has only two usable sides (the ± directions of its escape axis), so the connection topology must be an open chain, not the MST tree used for single-ended multi-point nets. The new diff_pair_multipoint.py:

• groups the pair's pads into (P, N) terminals and orders them as the shortest chain, penalizing orderings whose interior terminals would force a wrap-around leg
• routes leg by leg, with each continuation leg leaving a shared terminal on the opposite side from the leg that arrived — the chain passes "through" the pads
• resolves polarity per leg geometrically (pad swaps are never used — a swap at a shared terminal would break the already-routed leg), and validates every leg for P/N crossings
• rips out a failed attempt's legs and retries alternative chain orderings (the side constraints depend on routing order, so a reversed chain can succeed where the forward one corners itself)

On the LVDS converter test board, /DATA± (3 terminals) and /CLK± (4 terminals, passing through two terminals on the same IC) now route fully connected and KiCad-DRC-clean. A new regression test (tests/test_multipoint_diff_route.py) locks this in.

Board-edge clearance actually works now

Chasing a copper-to-edge DRC report from GUI routing uncovered a chain of issues:

• gr_poly board outlines were not parsed — boards whose Edge.Cuts outline is a polygon (rather than gr_rect/gr_line/gr_arc) had no known bounds, so edge-clearance blocking silently did nothing for them.
• The GUI's differential tab never passed the edge clearance to the router, and with the "Edge Clearance" checkbox unchecked the other tabs ignored the board's min_copper_edge_clearance rule too. All routing tabs now share one rule: explicit control when enabled, otherwise the board's minimum copper-to-edge constraint whenever "Obey design rule constraints" is on.

Other fixes

• Micro-gap welding: sub-0.01mm bridge segments produced by sub-grid connector geometry were silently dropped, leaving hairline gaps between a connector and its track; simple chain bridges are now welded shut (junction fragments are still dropped untouched).
• Centerline endpoint un-snap: grid snapping could bias a bare-pad connector fan half a grid cell toward one pad of the pair and graze its corner by a few µm; the generated geometry now uses the exact setback positions.
• tests/README.md documents how to cross-check routed boards with KiCad's own DRC via kicad-cli (not part of the test suite, since KiCad may not be installed) — including the --refill-zones gotcha and why netclass-mismatched routing parameters show up as violations.

[drandyhaas]

Update — June 9 (evening): polarity resolution by shortest route

Following up on the multi-point work — polarity mismatches are now resolved by competition between the two available mechanisms, and the result on the LVDS converter board speaks for itself:

CLK± spans 4 pad-pair terminals (connector → termination → two IC pin pairs; note the swapped IC pins 6/7), DATA± spans 3 — every leg enters its terminals directly, no detours.

What changed

• Pad swap vs connector flip, shortest wins. When a leg's P/N polarity differs between its ends and polarity fixing is enabled, the router routes all viable resolutions — swapping the pad nets at one end, or taking the connectors out the opposite side at either flippable end — and keeps the shortest clean route. If only one mechanism succeeds, it's used. Previously the first viable resolution was accepted, which could mean a 20mm wrap around a connector when an 11mm direct entry existed. On stub-based boards (no flippable ends) the swap commits directly with zero extra routing cost, so existing flows are unchanged.
• Pad swaps now allowed in multi-point chains — at safe terminals only. Each leg may swap pads at its chain-fresh terminal (never a shared terminal that already has a routed leg attached); subsequent legs re-orient to the swapped nets, and ripped chain attempts undo their swaps. This eliminated CLK's old wrap through the IC: a 12.95mm swap route beat two ~21.4mm flip wraps.
• Both-ends flip comparison for --no-fix-polarity mode (the plugin GUI default): when both ends can flip, both candidates are routed and the shorter wins.
• Sub-grid clearance fix for diff pairs: pad keepouts in diff-pair obstacle maps get a slightly larger corner/diagonal buffer, covering the ~10µm shortfall that the P/N offset geometry could shave off diagonal passes by round pads (KiCad-DRC near-misses at PTH connector pads). Scoped to diff-pair maps only — single-ended routing and plane generation are untouched.
• Together with the board-edge keepout chain from the earlier update (gr_poly outlines + GUI plumbing), the full board now routes KiCad-DRC-clean with the 0.5mm copper-to-edge rule enforced, in both polarity modes.

The multi-point regression test now runs five scenarios: each pair with fixing on (asserting the expected length-comparison winner — flip for DATA, pad swap for CLK) and with --no-fix-polarity (asserting pad swaps never occur), plus the sequential two-pair flow. The full suite (single-ended boards, planes, keepouts, guide corridors, LVDS pipeline) matches its pre-change baselines exactly.

[drandyhaas]

Update — June 10: Claude in the plugin GUI, and a multi-point crossing fix

Two threads today: the plugin grew a full AI assistance layer driving the project's Claude Code skills from inside KiCad (#34, #39, #40, #53 — PR #52), and the multi-point diff-pair work from yesterday shook out one more correctness fix (#56).

Claude tab: plan → review → execute (#40)

The routing dialog has a new Claude tab that spawns claude headless (streaming a live transcript of every tool call into the GUI) and brings results back into the dialog's own controls:

• Plan Routing runs /plan-pcb-routing and gets back a machine-readable JSON plan. The plan's parameters land in the tabs they belong to (track widths on Basic, pair selection + gap on Differential, net→layer assignments on Planes, ...), and the steps appear as a checkable list. Run Selected Steps executes them sequentially through the tabs' own in-process machinery on the live board — Claude only plans; the GUI routes. Steps get live status marks, completed steps uncheck so a stopped run resumes, and the transcript + plan persist across dialog reopens.
• Review Routed Board (/review-routed-board) and Diagnose Routing Failures (/diagnose-routing-failures, fed the Log tab's content) give post-route QA and failure root-causing from the same tab.
• Model and effort dropdowns control every AI run and persist with the dialog settings; saved values that no longer exist revert to Default.

Per-field "Ask Claude" buttons (#34, #39, #53)

Each analysis skill is also wired to the field it feeds, with validation between Claude and the controls (unknown nets/layers dropped with logged notes, garbage rejected):

• Power Nets / Power Widths (Basic tab) ← /analyze-power-nets
• Check Stackup (Layers section) ← /recommend-stackup
• Differential pair verification (Differential tab) ← /identify-diff-pairs — checks pairs confirmed by pin function, unchecks name-matching false positives
• Net → plane-layer assignments (Planes tab) ← the new /recommend-plane-mappings skill (GND adjacency for return paths, GND/VCC pairing, 2-layer pour advice), with a replace/merge prompt
• GND via Max Distance (Planes tab) ← /find-high-speed-nets

Analyses run on a temp snapshot of the live board, so unsaved edits are always visible to Claude and the board file is never touched. The button-to-skill map is documented in docs/claude-skills.md. Version bumped to 0.15.10 (release pending).

Multi-point diff pairs: crossing legs are now rejected (#56)

Field testing the Claude plan flow found a real router bug: a chain leg was only validated against its own P/N crossing — whether it crossed previously committed legs relied on the obstacle map, which deliberately exempts corridors at shared terminals so the opposite-side setback can leave. When a GND stitching via blocked the channel next to a termination resistor, the forced wrap-around leg crossed the earlier legs inside that exemption: committed P/N shorts plus self-crossing loops.

Legs are now checked against all committed legs' segments after routing (terminal-pad touches excluded — only proper crossings count); a crossing rejects the leg and the existing alternative-chain-ordering retry takes over. On the repro board: with polarity fixing the pair routes cleanly around the via (zero crossings, ~30mm instead of the looping ~45mm); with --no-fix-polarity it now fails honestly — all orderings rejected, zero segments committed — instead of shorting. The repro board ships as a regression fixture with two new test scenarios (7/7 passing).

Plan ordering: signals before planes

The #56 trigger also reshaped /plan-pcb-routing's recommended order: fanout → diff pairs → signals → planes (+ GND return vias) → repair. Plane stitching vias can relocate around routed tracks; a diff pair cannot relocate around a badly placed via. The flip side is mandatory: the signal routing step must exclude the plane nets (--nets "*" "!GND" "!VCC") so they aren't routed as tracks — the skill's workflow, the GUI plan schema, and the plan executor (which now understands ! exclusion globs) all enforce it. Live-validated: the LVDS board's plan came back route_diff → route(["*", "!/GND"]) → route_planes(/GND→B.Cu) with zero plane-net overlap.

[drandyhaas]

Update — June 10 (evening): the Claude tab in action, a 6.4× obstacle-map speedup, and hardening

The Claude tab, working end to end

The plan → review → execute flow from this morning's update, on the LVDS converter board — /plan-pcb-routing ran for ~2 minutes, filled the tabs, and produced the checkable step list (note the plan's !-exclusions on the route step so the GND plane net isn't routed as tracks, and the parsed JSON plan in the transcript):

Refinements that landed after field use: the transcript and step list (with status marks and check state) persist across dialog reopens and only clear when a new Plan Routing run starts; Review/Diagnose runs append under a separator instead of wiping the log; and analyses run on a temp snapshot of the live board (kipy-style save-a-copy semantics), so unsaved edits are always visible to Claude, the user's file is never touched, and the save-over-open-file crash class is gone.

Obstacle map rasterization: 6.4× faster (issue #35)

Profiling issue #35's "rayon for base map rasterization" idea found the premise didn't hold: the rasterization was pure Python, calling into the Rust map one cell at a time — 13.1 million Python→Rust FFI crossings per build on a dense board. There was nothing in Rust for rayon to parallelize.

The fix was numpy batching into the Rust batch APIs that already existed: base obstacle map builds went from 1.72s → 0.27s on a fully-routed 5,973-segment board (the reroute scenario where it dominates), and the per-net obstacle cache from 0.49s → 0.34s. Equivalence was proven the hard way — the Rust map reference-counts cells, so the batched code emits the exact same multiset of cell additions as the old loops (verified against the legacy implementation across three boards, plus a bit-identical full-board route: same nets, same 1,390,741 A* iterations). Pure Python, so no Rust rebuild ships. The genuine rayon candidates (parallel forward/reverse probes, parallel rip-up evaluation) stay open in #35.

Hardening

• Close-during-run crash fixed: closing the dialog while a Claude run streamed (e.g. Review Routed Board) crashed pcbnew — background-thread wx.CallAfter callbacks landing on destroyed widgets, plus an orphaned claude subprocess. The tab now shuts the run down on window destroy, and every main-thread callback is liveness-guarded.
• Multi-point regression fixture: the Diff router can loop back and cross its own pair when detouring around obstacles near termination resistors #56 board (GND stitching via blocking the diff-pair channel) ships in kicad_files/ with test scenarios asserting both outcomes — clean routing around the via with polarity fixing, and honest failure with zero committed segments without it.

IPC branch synced

The ipc-migration branch (KiCad 10 IPC plugin) now carries the full Claude integration — the one real porting item was the board snapshot, which maps cleanly onto kipy's Board.save_as() (SaveCopyOfDocument: the open document keeps its file association).

All of this is on main as v0.15.10, pending release.

[drandyhaas]

Update — June 22: the real-world stress-test era (v0.15.11 → v0.15.15, 80+ fixes)

Since the June 10 update the project has been through one dominant theme: stress-testing the router against 45 real-world open-source KiCad boards and grading every result against the board's own human routing. That program (its own write-up and full per-board scorecards live in discussion #117) has driven 80+ fixes and five releases (v0.15.11 → v0.15.15), and v0.15.15 is now live in the official KiCad PCM (merged via gitlab.com/kicad/addons MR !607), so it installs straight from KiCad's Plugin & Content Manager.

Rather than re-list all 80, here are the changelog-level highlights.

New capabilities & features

• Dense-BGA under-pad escape engine (--escape-method underpad, bga_fanout silently drops deep interior balls on large fully-populated BGAs #122). Fully-populated BGAs were silently dropping their deepest interior balls — the channel-template fanout has nowhere to put them. The new engine drops a via in each signal pad and escapes straight under the pad field on an inner layer (SMD pads only block their own layer). It clears every dense board the channel router couldn't (ulx3s 22×22, cparti 24×24 Artix-7) on 4 layers → 0 dropped, and is now available for QFN / fine-pitch edges too (qfn_fanout: add diff-pair via-drop / underpad escape (port bga_fanout's find_diff_pair_escape + --escape-method underpad to QFN) #164).
• DRC graded at the manufacturing floor, not the net-class stick (Per-net/region clearance: global --clearance forces board-wide DRC when escaping fine-pitch parts #111 / Routing uses netclass via_diameter for ALL vias (behaves like a max) -- need a smaller working/escape via #115). KiCad net-class track_width/via_diameter are drawing defaults, not DRC minima — the tools now read the DRC-enforced Board Constraints and emit a small working via down to min_via_diameter, then grade DRC at the real fab floor. On fine-pitch boards this turns hundreds of phantom escape "violations" into the handful that are real (e.g. smartknob 282 → 0).
• --output / named output alias for route.py and route_diff.py (Add --output/-o alias for the output file in route.py / route_diff.py (and unbind -o from --ordering) #136).
• Placement repair — place_optimize.py (greedy-quench refiner) and place_route_loop.py (router-in-the-loop). The from-scratch constructive placer was removed; the tool is a repair pass, not a polisher.
• Grid-independent routing cost knobs — the cost flags are now mm-based, so behaviour no longer shifts with --grid-step (Make routing cost knobs mm-based, independent of grid step #69).
• New skills / analysis — recommend-plane-mappings (net→plane-layer with SI rationale), and RF/antenna + controlled-impedance detection wired into high-speed-net routing (Plan does not detect RF/antenna feeds as impedance-controlled (50Ω single-ended) nets #139).
• New checkers & utilities — check_pads.py (mis-modelled pad geometry), check_orthonormal.py (stray diagonal segments), check_cycles (redundant copper loops), fix_kicad_drc_settings.py (strip stock-default DRC noise), plus compare_to_original.py grading against the human board.
• Verified Python API docs — runnable, example-checked API reference for the parser/writer/config/net-analysis modules.
• Stress harness + /stress-test-router skill — downloads, normalizes, strips, re-routes and grades the corpus headlessly, with full command-replay (redo_*) for LLM-free reruns.

Major bug fixes (grouped)

• Parser robustness — power/mixed copper layers, parenthesized layer names ("In1(GND).Cu") and a lone ( in a property value swallowing later footprints (kicad_parser: pads duplicated ~4x and arrays detected by footprint name, not geometry #113), oval/slot drills misread as SMD, locked tracks now honoured as obstacles (Locked tracks are ignored as obstacles (router lays copper through them #150), custom pads modelled by their real copper extent, and the big one: rotated SMD pads were modelled 90° off their true shape, boxing in every pin of a rotated row — fixed in v0.15.14 (bga_fanout: BGA placed at a non-orthogonal angle is not handled (grid + escape analysis are global-frame) #137), with check_pads.py to catch the rest.
• Fanout — rotated / non-orthogonally-placed BGA collision made exact (bga_fanout: BGA placed at a non-orthogonal angle is not handled (grid + escape analysis are global-frame) #137), escape via/track now sized to the actual pitch budget with a warning when they don't fit (BGA fanout escape stubs graze adjacent fanout vias by ~13µm (geometric: via Ø0.5 won't fit 0.8mm half-pitch at 0.1 clearance) #158), and LGA / fine-pitch land-grid arrays recognized as fanout candidates (LGA packages are not fanout candidates (plan-pcb-routing skill + fanout filter), stranding interior LGA pads #144).
• Diff pairs — real P/N shorts that used to ship as "routed" are now caught and rejected (route_diff: reports a pair routed while its P and N traces cross 4 times (real shorts) #102); USB-C / coincident-flip-pin connector clusters route (route_diff: multi-terminal differential pairs (USB-C dual-row pattern) systematically fail #90); the connector launch path was reworked (pad-edge launch, min-cost terminal pairing, no partner-pad grazing) and verified end-to-end on a real board (Tigard FT2232H USB, route_diff connector/setback segments graze the PARTNER net's connector pad (obstacle map excludes the whole pair) #165); plus broad name-detection (DP/DN, P0/N0, TXP/TXN, hierarchical globs, crystal guards — route_diff.py pair detection misses common naming conventions (DP/DN, trailing-digit P0/N0) and silently no-ops on comma-separated --diff-pairs #143/list_nets --diff-pairs false-positives on crystal/oscillator P/N net names (single-ended, not differential) #145/Diff pairs with names like TXP/TXN don’t pair up #151/Diff-pair glob '*_P' fails to match hierarchical (slash-separated) net names #120).
• Routing core — post-route dead-end / orphan-stub cleanup and honest reconciliation of reported success vs. the written board (route.py multipoint: orphan dead-end stubs and same-net self-crossings on successfully routed nets #84/Router reports net fully routed but produces disconnected trace segments #8); the geometric fix_self_intersections + collapse_appendices passes were removed outright after they traded one short for another (Terminal connector to off-grid fanout-stub end is an unchecked long diagonal that crosses foreign vias (keks /SRAM_A6 232µm over /SRAM_A17 via) #159/Same-net self-crossings: find the source and remove them cleanly (delete-only, not geometric extension) #162); tighter via obstacle geometry and same-net via-in-pad reuse.
• Power planes — rip-blocker plane-repair that re-routes a blocking net to free a stranded pad (route_planes: secondary power plane (Voronoi multi-net) starves the smaller net's peripheral pads #112), out-of-outline plane vias/traces fixed (route_disconnected_planes places zone-fill segments and stitching vias outside the board outline #119), through-hole pads in another net's region now tapped (route_planes: Voronoi multi-net planes silently skip TH pads that land in another net's region #107), and stitching-via hole-to-hole spacing enforced (Same-net vias placed below the hole-to-hole drill minimum #125).

GUI / Claude tab

The CLI/GUI parity discipline held throughout (documented as a standing rule): the QFN under-pad escape, plane-repair rip-blocker + distant-pad-trace repair, per-step plan-param re-application, and a repair_planes plan action all landed in the plugin alongside their CLI counterparts.

---

Full detail and the per-board stress scorecards are in #117; everything above is on main and released through v0.15.15.

[drandyhaas]

Update — June 22 (later): DRC settings that match the route, and a sub-clearance grazes sweep

v0.15.15 is now live in the official KiCad PCM (merged via MR !607), so it installs straight from the Plugin & Content Manager. Since that release the work below has landed on main, heading for the next release.

KiCad DRC now matches the clearances the router actually used (#160)

The long-standing annoyance: open a freshly-routed board in KiCad, run the DRC, and get hundreds of false positives — because the project file carries KiCad's stock-default design rules, not the floors the board was routed to. Routing now writes the board's DRC design rules back to match: a complete Default net class plus the full constraint set (clearance, hole-to-hole, copper-to-edge, min via/track), with non-routing categories (thermal, courtyard, solder-mask) demoted. So the interactive DRC shows the same honest count our own check_drc grades. It's auto-invoked after routing from both the CLI and the GUI (shared fix_kicad_drc_settings logic), and constraint floors are taken as min(routing param, existing board minimum) so a stricter rule you set is never loosened.

A new grading method, and the sub-clearance grazes it caught

Grading runs now compare at the minimum routed clearance with a whole-set A/B replay tool (ab_replay_grade.py, --regrade). That tightened lens exposed a cluster of sub-clearance grazes the obstacle map had been rounding away — all now fixed:

• grid-quantized clearance / via keep-out radii were floored where they needed ceiling (ceil the floored radii in precompute_via_placement_obstacles (grid-quantization clearance) #154/route_planes: own routing-obstacle build floors expansions (route_planes.py:662,668) #155)
• terminal/endpoint and plane-tap connection segments grazed foreign pads (Terminal/endpoint connection segments graze foreign pads #157)
• the track-block obstacle lacked the diagonal margin the via-block already had, and kept out from the configured net width instead of a segment's actual width (route.py grazes a diagonal diff-pair trace: track-block obstacle lacks the diagonal margin the via-block has (eis /PMOD_A9 over /DDMI_CK_P) #172)
• board-edge via keep-out swept only the track band, not the full via band (route.py places vias too close to the board edge (esp_prog: Net-(R3-Pad2) vias 0.103mm over edge clearance) #170)
• multipoint tap rip-up re-routed a victim straight through an already-placed foreign via (route.py multipoint tap-retry re-routes a net through an already-placed foreign via (eis /RP_SS over /CSPI_SO via, 0.27mm overlap) #171)

Net effect: the real different-net shorts and via-over-track/edge overlaps that remained on the densest boards (eis, daisho, esp_prog) — down to tens of microns — are caught and cleared (#169/#174).

Diff-pair regression fixes & QFN escape

• The connector launch-path rework briefly regressed two boards' USB source escape (esp_prog Regression: esp_prog USB diff pair /D_P//D_N source escape blocked (routed Jun 18, fails on current HEAD) #166, watchy Regression: watchy USB_D+/USB_D- diff pair fails terminal/launch escape ('no valid position at any setback/direction') #167) and overshot the setback past a long source pad — both fixed.
• A diff pair routed with sub-clearance spacing to its own test point (orangecrab Diff pair EXT_PLL+/EXT_PLL- routed with sub-clearance spacing to its own test point (orangecrab) #168) is now clean, including the stub layer-swap clearing the partner polarity's test point.
• QFN under-pad escape gained an alternative-stagger search + via-in-pad/off-pad mix, raising the escape fraction on crowded fine-pitch edges (Trouble escaping a diff pair from a crowded fine-pitch QFN edge, any tips? #161), and it now checks foreign tracks.

Full per-board detail is in #117; everything here is on main, pending the next tagged release.

[drandyhaas]

Update — June 23: decoupling-cap placement repair, and DRC-settings parity everywhere

Two threads landed on main since the last update.

Decoupling-cap placement repair (#130)

The one residual the dense-BGA under-pad escape (#122) couldn't fix on its own: on a fully-populated array, a decoupling cap sometimes sits exactly where a signal ball wants its via-in-pad, so the via and the cap pad overlap. A new repair pass fixes it by moving the cap instead of the via — after fanout it nudges each near-BGA decoupling cap or resistor off any foreign-net fanout via (and any foreign track on its side) and pulls its pad toward the nearest same-net ball, so a power/GND via dropped there later also lands on the cap. Caps (and resistors) move as little as possible, never overlap each other, and any that still can't clear are reported. Relatedly, bga_fanout now reports a drc_grazes field in its JSON summary (the output DRC'd at the fanout clearance), so even when every ball escaped, the plan-pcb-routing flow can catch a leftover via-over-track graze and retry the fanout with a smaller via / thinner track.

• CLI: place_fanout_clearance.py (run after bga_fanout.py).
• GUI: an "Optimize decoupling cap placement" checkbox on the BGA fanout tab, with a "Cap Placement (advanced)" box exposing the tuning knobs (capture radius, near margin, search step, max displacement / cap / growth, max passes, cap-ref prefix, allow-rotation).
• The Claude plan auto-adds it as a step after BGA fanout.

On ulx3s U1 (22×22, 0.8 mm) it takes the fanned board from 4 via-in-pad overlaps to fully DRC-clean, tidying 19 caps toward same-net balls.

DRC-settings write-back now covers every routing entry point (#160)

The "make KiCad's interactive DRC match what we routed to" auto-fix (from the last update) is now wired through everywhere, not just route.py/route_planes.py:

• route_diff.py and route_disconnected_planes.py now auto-fix too (they previously didn't — route_diff had no DRC write-back at all, so a diff-pair-only run still opened with stock-default noise).
• GUI: a single "Fix DRC settings after routing" toggle on the Basic tab now controls all routing actions — single-ended, differential pairs, and plane create and repair — through one shared setting (previously the differential and repair-plane paths were inconsistent).
• keep-thermal: a new --keep-thermal flag on all four routing CLIs (and a "Keep thermal-relief DRC severity" checkbox on the Advanced tab) leaves starved_thermal at its original severity instead of demoting it to a warning, for boards where you want that check to stay an error.

Both front-ends share the same target-computing logic and only differ in how they apply it (.kicad_pro file vs. the pcbnew API), and constraint floors are only ever loosened toward the routed values, never tightened below a stricter rule you set.

Full per-board detail is in #117; everything here is on main, pending the next tagged release.

[drandyhaas]

Update — June 24: comb-pad geometry, coupled BGA diff pairs, and a routing-speed pass

A batch landed since the June 23 update — much of it driven by re-running the set-1 stress boards and categorizing what still failed — and it shipped as v0.16.0 (the first release on the 0.16 line), with a follow-up v0.16.1 right behind it (its additions are in the last section). Both bundle a rebuilt Rust router with fresh Linux / macOS (arm64 + x86_64) / Windows binaries on GitHub Releases, so the new Rust-accelerated blocking analysis (below) works in the installed plugin.

Real pad geometry: comb/finger custom pads (#188)

A power MOSFET's large exposed source/drain pad is a notched comb/finger polygon, but the model kept only its size_x × size_y bounding box — filling the notches solid and walling in the gate/source pads that route through the channels. On bitaxe_ultra that left four signal/power nets plus five GND plane pads unroutable, all reporting the misleading "no rippable blockers found." The obstacle map and DRC now rasterize the true copper outline — parsed from the file's gr_poly primitives, and in the GUI from pcbnew's effective polygon (degrading safely to the bounding box headless) — and those nets route.

Coupled differential-pair escape under a BGA (#182)

The dense-BGA under-pad escape engine (#122) used to route both halves of a diff pair single-ended, so route_diff couldn't re-pair them. It now escapes each pair coupled — P and N exit on one shared layer at the diff spacing (edge pairs via-free on top, deeper pairs end-on on an inner layer), falling back to single-ended only when no coupled corridor fits. On glasgow (BGA U30, 0.8 mm) all 13 FPGA Z-pairs now escape coupled and route DRC-clean (was 0).

Routing robustness

• Via-in-pad unblock. A signal pad boxed against same-layer copper now drops a via in its pad and escapes to a free layer — generic across single-ended, diff-pair, and plane routing, triggered when a net gets stuck, with failed via sizes memoised so the retry doesn't blow up.
• A fine-grid retry that routed a different net through an existing trace — a real inner-layer short — is caught by re-routing the nested-cascade victims that cross a kept tap (route.py: different-net SEGMENT-CROSSING on an inner layer — fine-grid retry routes through an existing trace (real short) #186).
• The multipoint pad counter that under-reported connected pads (flagging as disconnected pads that check_connected confirms whole) now derives its tally from the final-board union-find (route.py multipoint pad counter under-reports: counts pads disconnected that check_connected confirms connected (inverse of #8) #184).
• Plane repair no longer boxes in nearby protected-net pads (route_planes/route_disconnected_planes: stitching boxes in nearby protected-net pads, leaving them permanently unconnected #180): the distant-trace reach is unified to --max-search-radius, a stranded pad traces to an escaped same-net SMD pad or to existing plane copper before dropping a redundant via, and a fine-pitch repair retry ladder (smaller via, then finer grid) recovers pads the first pass leaves disconnected.
• Diff-pair detection: passive ± terminals (buzzers, Net-(REF-±)) no longer false-positive, and USB D+/D- carried on chip-path (hierarchical) net names now pair (list_nets --diff-pairs: false positive on buzzer +/- terminals; misses USB D+/D- with chip-path net names #181).
• Literal !-prefixed (active-low) net names are now selectable instead of being parsed as exclusion patterns (route.py --nets: literal '!'-prefixed net names parsed as exclusion patterns (active-low nets unroutable) #177).

Layer balance & DRC grading

• On dense 2-layer boards the default B.Cu layer-cost over-biased F.Cu (excess vias, poor balance), so --layer-costs is exposed and the plan now derives per-layer costs from the planned plane assignment (route.py: 2-layer default B.Cu layer cost (3.0x) over-biases F.Cu -> poor layer balance + excess vias; add --layer-costs #178 / plan-pcb-routing: derive route.py --layer-costs from the planned GND/power plane layer assignment #185).
• The fab-floor track-width and via/hole-size checks now grade against the fine-via floor, so small working-via escapes don't read as too-small violations (route.py: multipoint tap segments emitted at grid-step width, ignoring --track-width and the fab floor #176); and qfn_fanout reports a drc_grazes summary and the planner shrinks the stub width until the escape is clean (qfn_fanout: 45-degree escape stubs graze adjacent diff-pair pads at 0.4mm pitch (SEGMENT-SEGMENT) #179).

Faster

A routing-speed pass with no behaviour change: five hot Python loops in the DRC / fanout / obstacle paths were vectorized, the plane-tap local-window scan was spatial-indexed, keepout rasterization is clipped to the map window, and the blocking-obstacle analysis was ported to the Rust router (v0.16.1) with a C-level set intersection — large speedups on dense boards.

Housekeeping

A dead-code sweep removed 24 unused functions and dead imports (#187). The CLI/GUI parity discipline held throughout: the Claude plan tab now carries --layer-costs and the plane-repair grid-step into the GUI to match their CLI counterparts.

Also in v0.16.1

A few more changes landed in the follow-up release:

• route_diff --layer-costs — per-layer cost bias for coupled differential pairs, so a pair can be steered onto preferred layers the way single-ended routing already could (route_diff: support --layer-costs (per-layer routing cost), matching route.py / route_planes #193). It's wired through the GUI and the Claude plan's route_diff step, which can now also request impedance-controlled diff routing.
• Diff-pair detection no longer misreads a _t_ / _c_ infix (a DDR-style true/complement marker mid-name) as a differential pair when it isn't one (diff-pair detection: a _T_ / _C_ infix is misread as DDR true/complement, silently dropping real +/- pairs #192).
• More GUI/CLI parity — the impedance diff control, plane-repair --max-search-radius, and native KiCad rule-area keepouts all reach the plugin alongside their CLI flags.
• Stress harness — an A/B coupled-diff completion metric, per-step timing + peak-RSS capture, and a bounded-retry queue watchdog.

---

Full per-board detail is in #117; everything here is on main and released through v0.16.1.

[drandyhaas]

Update — June 26: v0.17.0 — exact swept-capsule clearance and a differential-pair escape rewrite

v0.17.0 is out (now the latest GitHub Release), bundling a rebuilt Rust core (crate 0.17.0) with fresh Linux / macOS (arm64 + x86_64) / Windows binaries.

Exact swept-capsule obstacle clearance (#173 / #156)

The biggest change under the hood. The obstacle map and DRC used to model a track or via keep-out as a grid-quantized, over-covered box — which is what the recent "floor-vs-ceiling rounding" and "diagonal margin" graze fixes were all working around. The clearance is now computed against the exact swept capsule of the segment/via at its real width — and the exact keep-out is the default (the old opt-in gate is gone), at route.py ↔ plane-router parity, with the rip-up blame map built from the same exact capsule (#203) and a check_drc same-net via-via check added. The net effect is fewer phantom clearances and less spurious over-blocking, so routes that legitimately thread a tight channel are neither flagged nor walled out. This is the Rust change behind the 0.17.0 crate bump.

Differential-pair escape, rewritten (#195 / #197 / #165)

The in-function hybrid escape was replaced by a direct-coupled-middle router: a pair's coupled middle routes on any layer, each leg drops its own escape via, and the terminal legs route point-to-point, so a pair now escapes and fully routes inside route_diff (including inner-layer launch, with the P/N offset side chosen to minimise terminal-leg crossings). On top of that:

• Boxed-endpoint escape now uses exact geometry, and an escape via must clear every obstacle by the real rule while reusing same-net holes (Hybrid diff escape: stock watchy USB_D coupled route blocked by surface-fanout congestion (escape via won't fit) #197).
• Under-pad-escaped diff pads that previously stranded now connect, via a via-reachable multilayer launch (feature: coupled diff-pair underpad escape for qfn_fanout (port the bga_fanout #182 logic?) #195 — QFN under-pad diff escape routes 2/2, connected, DRC-clean).
• A 3 mm (λ/10 @ 5 GHz) electrical floor on the coupled-length test means legs with no real coupled section go single-ended instead of being forced into a coupled corridor, and the GUI's Differential tab gained a "Hide short routes" toggle.

Fanout & routing core

• qfn_fanout ramps the fan angle to 45° at the corners to spread the stub tips on crowded fine-pitch edges (qfn_fanout: spread adjacent stub endpoints apart (more tip clearance) while staying on grid #200), and via-in-pad is clamped to its pad edge at placement (Fanout via-in-pad larger than its pad -> VIA-SEGMENT grazes (156 on keks) #202).
• The via-in-pad escape is now always on (the DISABLE_VIA_ESCAPE gate was removed, Remove the DISABLE_VIA_ESCAPE gate; always run the #189 via-in-pad escape #201), and phase3 got a cycle guard so a net's rip-up can't rip its own ancestors.
• Stress harness: a redo_diff_stage.py replay for just the fanout + route_diff stages, graded at the manifest clearance floor.

---

Full per-board detail is in #117; everything here is on main and released as v0.17.0.

[drandyhaas]

Update — July 1: v0.17.3 — differential-pair hybrid legs, fab-floor cost tiers, and DRC graded at what you routed to

v0.17.3 is out (now the latest GitHub Release), bundling fresh Linux / macOS (arm64 + x86_64) / Windows binaries. This post also folds in the two point releases since the v0.17.0 update that never got their own writeup — v0.17.1 (Rust crate → 0.17.1, forbidden-layer support) and v0.17.2 (a binary rebuild). v0.17.3 itself is Python-only on the 0.17.1 crate. Much of this batch came out of re-running the stress corpus and categorizing what still grazed or disconnected.

Differential pairs — the hybrid leg, and coupling that holds clearance

The direct-coupled escape from 0.17.0 got a lot of follow-through, mostly around the hybrid leg (a pair's coupled middle routes on one layer; each leg then breaks out to its terminal):

• The hybrid leg now couples on the terminal layer, as close to the pad as possible, graze-free (Route congested-BGA multipoint diff pairs via per-leg hybrid (CK1) — layer scheme + leg-endpoint TODOs #243), reuses the coupled-middle near-end via instead of stacking a clashing one beside it (Coupled diff-pair P/N still overlap below clearance at bends (residual of #215, different mechanism) #248), picks the non-crossing polarity (Diff-pair offset/leg tracks not validated against foreign copper (inter-pair crossings/grazes) #246/Coupled diff-pair P/N still overlap below clearance at bends (residual of #215, different mechanism) #248), and never emits inter-pair offset/leg crossings — the standard route is preferred and the hybrid is a fallback (Diff-pair offset/leg tracks not validated against foreign copper (inter-pair crossings/grazes) #246).
• The connectivity gate checks the leg's own terminals, not the whole net, so a layer-blind skip can no longer leave a terminal orphaned while reporting success (route_diff: coupled differential-pair P/N traces overlap below clearance at bends (SEGMENT-SEGMENT) #215/HDMI TMDS pairs route single-ended: fixed hybrid connectivity-gate scope + stub-walk segment-drop (2/6->3/6); residual is multi-pair congestion — set-4 fpga_sdram #250); get_stub_segments follows the closest connected segment (HDMI TMDS pairs route single-ended: fixed hybrid connectivity-gate scope + stub-walk segment-drop (2/6->3/6); residual is multi-pair congestion — set-4 fpga_sdram #250).
• Coupling that used to pinch or graze is fixed: the grid→float join that squeezed P/N at the junction is collapsed, a coupled route that self-overlaps falls back to the hybrid, a leg grazing its partner below clearance is rejected, and single-ended-style cleanup now runs on diff-pair copper too (route_diff: coupled differential-pair P/N traces overlap below clearance at bends (SEGMENT-SEGMENT) #215). Bare-pad target-swap vias are clearance-guarded and partner pads re-added as via keep-outs (route_diff: coupled diff-pair layer-transition vias not re-validated against partner via body / foreign pads (VIA-VIA / PAD-VIA) #241).
• AC-coupled length matching (route_diff: AC coupled diff pairs split by series caps are length matched per side, not end to end #196): length/skew matching now works across a pair split by series caps — the concatenated P-vs-N length is measured through the cap (XNet) and matched end to end.
• Meander clearance (length_matching: meander clearance uses base track_width, not the net's actual (impedance/power) width #175): length-/time-match meanders now reserve keep-out from each net's actual (impedance / power) width rather than the base track width, and stay inside the board outline instead of printing off the edge.
• bga_fanout half-edge pairs (bga_fanout: differential-pair escape stubs cross each other (SEGMENT-CROSSING) #242): a half-edge diff pair converges on the inner pad's own side without crossing or loop-back, and pairs whose fanout stubs already self-overlap are skipped.

Fab floors as cost tiers, and DRC graded at what you routed to

• Fab cost tiers (Model fab floors to the JLCPCB spec with cost tiers (standard vs advanced) + pad/via hole-to-hole split #237). Manufacturing floors (track / via / hole) are now a standard and an advanced ladder selectable with --fab-tier (CLI + GUI), plus a --fab-overrides file for a specific fab. Parameters below the floor now warn and pin to the floor instead of aborting the run, and the 0.30 / 0.15 fine-via rung is back on the standard ladder.
• Clearance auto-grading (route_diff single-ended fallback places vias below clearance to foreign pads (PAD-VIA) #226). Routing propagates the minimum clearance it actually used, so check_drc auto-grades at the routed floor — no more phantom sub-clearance grazes from grading stricter than you routed. Power-tap clearance also steps down to the fab floor.
• Holes & pads (Reconcile value-divergent hard-coded constants (centralize where intended) #229 / Router routes tracks across NPTH mounting holes (real DRC error); check_drc has no copper-to-hole check #233 / Parser: custom pads with gr_circle/gr_line/gr_rect primitives fall back to bounding box (phantom DRC + over-blocking) #232 / check_drc: no pad-to-pad clearance/short check (misses overlapping component pads KiCad flags) #234 / check_drc: board-edge check uses bounding box (not real Edge.Cuts outline) and skips pads — misses copper in cutouts/slots #236). Hole-to-hole and NPTH-to-track floors set to JLCPCB spec (0.20 mm); routed tracks are kept off NPTH drill holes with a new copper-to-hole DRC class; custom-pad primitives (gr_circle / gr_rect / gr_line) are modeled by their true outline, not a bounding box; a pad-to-pad check and a real board-outline edge check were added; check_drc is faster.

Grazes and cleanup that don't disconnect

• Foreign-pad- and foreign-track-grazing segments are pruned only when the net stays connected; load-bearing grazes are re-bent instead of cut, the detection extends to foreign vias, and graze cleanup now runs in the plane routers too (route/repair tracks laid below clearance to a foreign component pad (PAD-SEGMENT) #224).
• Fixed several cleanup passes that could silently disconnect a routed net: prune-vs-sweep disagreeing on via support (route.py: completion regressions on 10 boards after #173 clearance tightening; 2 are pure losses (tinytapeout_qfn, free_dap) #209), the dead-end sweep keeping useless plane-repair stubs via false anchors (route_disconnected_planes / post-plane routing leave clearance violations (SEGMENT-SEGMENT, VIA-SEGMENT, PAD-SEGMENT) #216), the output writer preserving stale input copper (Output writer preserves a processed net's stale input copper (can cross newly-routed nets) #220), and a plane via-map ref-count desync in the rip path (route_planes: GND/power plane tracks+vias graze the via field under congestion (the diff-pair-dense 'DRC regression') #208).
• Reverted layer-swap vias no longer leak into route_diff output (route_diff: coupled diff-pair vias placed below clearance to neighbouring drills/tracks/pads (VIA-DRILL-HOLE / VIA-SEGMENT / PAD-VIA) #221); a layer swap that would drag a stub across foreign routed copper is rejected (route.py reconnect leaves a different-net track-to-track crossing when a net fails to route (SEGMENT-CROSSING) #238); a diff-pair escape via grazing a foreign pad shrinks to fit rather than disconnecting the net (route.py: coupled diff-pair via placed 0.039mm too close to its pair-partner's pad (glasgow residual after #208) #212).

Steering — forbidden layers

• --layer-costs now accepts any negative value as "forbidden" (Through-via barrels not checked against copper on non-routing (intermediate) layers in subset-layer routing #206): that layer stays an obstacle (its copper still blocks vias, and through-vias may span it) but takes no routed copper. CLI + GUI.

Fanout & decoupling caps

• bga_fanout fans dense power rails instead of skipping them as phantom planes (bga_fanout: leaves inner-core balls of high-pin-count power rails unescaped (daisho, cparti) #218); via-grazing caps the cost descent leaves stuck are relocated (bga/qfn fanout: escape vias violate clearance to neighbouring pads (esp. cap pads); cap-placement remedy incomplete on dense boards (PAD-VIA) #213); a cap move that would slide a pad onto a foreign-net component pad is rejected (place_fanout_clearance moves a cap onto a foreign component's pads (creates a short) #235); via-spacing re-routes a net that dropped same-net vias too close together (route.py: router doesn't enforce same-net via drill hole-to-hole (VIA-DRILL-HOLE) #230); fanout escape-stub widths clamp up to the fab track floor (fanout: escape stubs laid below the fab minimum track width (TRACK-WIDTH) #223) and avoid grazing a foreign pad just outside the escape window (qfn_fanout: escape trace grazes a foreign pad (PAD-SEGMENT) and escape vias violate hole-to-hole (VIA-DRILL-HOLE) #214).

Robustness & housekeeping

• Crash fixes: a NameError in pcb_modification (Fix NameError: import Dict in pcb_modification.py #247), a SameFileError on route_diff --overwrite when no pair routed (Fix SameFileError in route_diff.py --overwrite when no pair routes #249), and a TypeError on failed_multipoint dicts (Fix TypeError in place_route_loop when a multipoint net fails to route #251); Python 3.9 support restored in install_plugin.py; diff-pair and single-ended rip-up ancestor cycle-guards.
• Planes: cross-layer SMD pad targets rejected as tap destinations; route_planes / route_disconnected_planes sped up (perf: speed up route_disconnected_planes / route_planes (now ~32% of stress-redo compute, and slower than before) #225).
• Stress harness: the no-LLM redo replay is pruned to the file-dependency chain by default (redo_stress_test: prune the manifest to the file-dependency chain (skip superseded/dead-end retries) instead of replaying verbatim #231), diff-stage replay gained parallel --jobs/--stagger, and a set-4 FPGA+SDRAM board was added. Verification conventions (grade DRC at the routed clearance, connectivity is orthogonal to DRC, deterministic-but-UUID outputs) are now documented in CLAUDE.md.

Versions

• v0.17.1 bumped the Rust crate to 0.17.1 (forbidden-layer support); v0.17.2 rebuilt the stale binary; v0.17.3 is Python-only on the same crate. All ship prebuilt Linux / macOS (arm64 + x86_64) / Windows binaries via GitHub Releases. Currently at v0.17.3.

Full per-board detail is in #117; everything here is on main and released as v0.17.3.