🔧 v0.19.0 — the 0.18.5 lane-discipline misstep, fixed (plus fractional track margins, impedance neck-down & keep-out-aware planes)

[drandyhaas]

Hey everyone! 👋

v0.19.0 is out — and it opens with an apology-shaped bugfix. 0.18.5 shipped a default we got wrong, and this release corrects it, then stacks a round of routing- and grading-quality improvements on top. Mea culpa first, then the new stuff.

📦 How to get it: download KiCadRoutingTools-0.19.0.zip from the Releases page, then in KiCad open Plugin and Content Manager → Install from File… and pick that zip. Prebuilt router binaries for Linux/macOS/Windows are attached — python build_router.py fetches them automatically, no Rust toolchain needed.

⚠️ First, the bad news: 0.18.5's lane-discipline default hurt routability

Remember 0.18.5's honesty section — "some boards now run ~1.5–3× longer" and "one net on one keyboard board still resists us"? Those weren't isolated quirks. They were the visible tip of a default we'd set far too aggressively.

0.18.5 bumped the direction-preference cost — the knob that nudges each layer toward horizontal-or-vertical "lanes," for that clean human-routed look — from 50 to 5000, a 100× jump. On open boards it produced gorgeous lanes. On dense boards it was a wall: a 5000× penalty on any off-axis move makes the short diagonal hops that diode/matrix nets need to weave between pads effectively unroutable, and the A* then burns its entire iteration budget failing them.

A full sets 6–11 A/B (real open-source boards) put numbers on it:

• +104 incomplete nets across the corpus; 26 boards worse, 2 broke entirely.
• One 65% keyboard board (kbic65) collapsed from 98.9% → 15.1% routed.
• route.py ran ~2× slower — grinding the full 2 M-iteration budget on nets it could no longer route.

0.19.0 dials the default back to 250 (~25% of a move) — enough to keep a real H/V lane nudge, without the cost-5000 wall. We confirmed it by isolating the single knob at fixed engine: kbic65 recovers 43/35 → 87/1 routed, bread_dcmotor 23/11 → 36/0, and the ~2× slowdown vanishes. If you routed a dense board on 0.18.5 and saw nets fail that shouldn't have — that was this. Re-route on 0.19.0.

✨ Then, the new stuff

🎯 Fractional per-layer track margins (Rust 0.19.0, #156). The router's swept-capsule blocked-check now takes a fractional margin — grid cells as a float, per destination layer — instead of an integer Chebyshev margin, and Python computes it as the exact extra half-width over a single stamp-side source of truth, so obstacle stamps and the margins that check them can't drift apart. Power and impedance widths flow through one unified path, and the new "phase-exact" margin kills sub-cell grazes the old ceil-and-round missed (a 77 µm graze on berkeley In2 that needed margin 1.0 where the bare math gave 0.988).

📐 Impedance neck-down (#465, env-gated, default on). An impedance-controlled net whose full-width route fails can now step down toward its nominal track width to complete — the same "connectivity over strict width" ladder power nets already use — necking near pads while keeping the wide impedance section wherever it fits. berkeley_obsidian DDR3 at --impedance 40 went from 70 clearance / 23 shorts → 8 / 0, all 44 nets connected. Set KICAD_IMPEDANCE_NECKDOWN=0 to restore strict-impedance-or-fail.

🏝️ Keep-out-aware plane fill (#477 + #478). KiCad's filler subtracts (copperpour not_allowed) rule areas from zone fill, splitting a plane into real islands — and our fill model was blind to them. On mokya, antenna/xtal keep-outs cut the In1 GND plane into pieces the model graded as one, and 3 of KiCad's 6 GND opens were invisible to our own connectivity checker. Now the fill model blocks copperpour-banned cells, so those splits surface as real islands the repair pass can join. #478 goes a level deeper: footprint-owned zones (KiCad 7+) were invisible to the text parser entirely — and 95 of 406 corpus boards carry them, almost always as copperpour keep-outs (including castor_pollux, the original #217 oracle problem board). Both fixes flow to the GUI for free — same shared extractor and fill model.

Full commit-level detail in the v0.18.5…v0.19.0 compare and the Rust changelog in rust_router/README.md.

Bug reports and feedback hugely welcome — open an issue or reply here. Happy routing! 🎉

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📜 The original v0.18.5 announcement (kept for the record)

Hey everyone! 👋

New release — v0.18.5. If 0.18.3 was about making the DRC trustworthy, 0.18.5 is about making the connectivity trustworthy — and then using that truth to finish boards. The headline: our hardest benchmark board, a 4-layer BGA audio SoC design that has resisted every release since this project started, now routes to 100% connectivity with zero DRC violations — graded by KiCad itself, not by us — from a fully scripted 11-minute chain. This announcement is the story of how chasing that one board uncovered (and fixed) a stack of bugs that turned out to affect the whole corpus.

📦 How to get it: download KiCadRoutingTools-0.18.5.zip from the Releases page, then in KiCad open Plugin and Content Manager → Install from File… and pick that zip. Prebuilt router binaries for Linux/macOS/Windows are attached — python build_router.py fetches them automatically, no Rust toolchain needed.

🕵️ The plot: our grader said 1 unconnected. KiCad said 8.

Mid-push, with the benchmark board at what we believed was a record "1 unconnected net," KiCad's own DRC reported 8. The seven extras were all power-plane balls under the BGA whose fanout vias our checker credited as plane-connected — and KiCad didn't. Chasing that disagreement found three nested problems, each hiding the next:

• The pour physically couldn't reach the vias. A zone pour needs 2×zone-clearance + min-fill-width of gap to pass between obstacles. Our pours were being written with a fixed 0.2 mm clearance default while the whole board routed at 0.1 mm — so no gap anywhere in a 0.65 mm BGA via field was passable, and every interior plane via sat in a tiny fill island that KiCad prunes as isolated. Every chain, all along.
• Our connectivity model couldn't see the problem. The zone credit was an outline test — "is this point inside the pour, with room for copper right here?" — which is exactly the question that credits a pruned island. KiCad's filler answers a different question: does fill actually flow here?
• The repair pass trusted the same blind model, so the machinery built precisely for this case skipped all seven balls with a clean bill of health.

✅ What 0.18.5 does about it: graders you can trust

• Zone clearance now follows the routed clearance by default (--zone-clearance still overrides), auto-stepping toward the fab floor when a dense BGA field it must serve can't be threaded — with a warning either way. On the benchmark this single change took the true unconnected count from 8 to 2.
• A real fill model (validator parity). Connectivity now rasterizes each zone at min-fill-width resolution, applies the pour's own clearance and KiCad's min-thickness opening, labels the fill into connected components, and credits two items as plane-connected only when they touch the same component — matching KiCad's pinch-and-prune semantics. It's lazy, cached, works without scipy (pure-numpy labeling inside KiCad's bundled Python), and adds ~0.1 s to a whole-board grade. Every consumer sees the same truth: the CLI checker, the GUI's net list ("hide connected" no longer hides a broken net), the router's own skip-this-net-it's-done gate, the repair machinery, and the cleanup passes.
• A kicad_unconnected.py oracle wraps kicad-cli pcb drc --refill-zones so stress grading reports KiCad's authoritative count next to ours. On the corpus the two now agree.

🚑 Rescues that actually stick

The last-chance per-net rescue pass got three fixes, one of which is embarrassing in hindsight:

• Successful rescues of partially-connected nets were being silently reverted. The rescue copper shipped in a results entry that the write-list's dedup pass didn't recognize as authoritative, so a later cleanup stripped it from the board — the log said "fully reconnected" and the file shipped broken. Rescue copper now folds into the net's authoritative result. This one fix recovered stragglers on boards across the corpus.
• Rescue ignores the advisory BGA keep-out zones. They're router policy, not DRC geometry — and for a windowed, verified, DRC-graded last resort they were only capable of preventing legal fixes. The benchmark's final signal net had a perfectly routable path (we hand-routed it to check!) that every retry walled off for exactly this reason.
• Rescue gets its own search budget instead of being throttled to the step's default iteration cap — that hand-routable path needs ~1.4 M A* iterations at the fine grid and was dying at 200 k with "no route."

🏝️ Plane repair that sees islands

The plane-repair step's region joiner discovered regions with a coarse 0.5 mm flood fill — which pours straight through a sub-cell pinch, merging a stranded island into the main region so no join is ever attempted. The joiner now gates its floods with the fill model's components: islands appear as real regions and get routed connections (tracks/vias), not just tap attempts. On one FPGA corpus board this found and joined 56 genuinely pinched islands — with KiCad DRC still reporting a perfect 0 afterward.

✂️ Seam dissolution: routes stopped shipping their scaffolding

A routed net is often a composition — a main edge routed early plus taps welded on later, or a diff pair assembled from escape legs and a coupled middle — and each piece was optimal against a board that no longer exists by the time the net completes. 0.18.5 re-asks the whole connection with one A* right when it completes, against the current board, and keeps the better answer (strictly-better, connectivity-verified, length-match groups exempt):

• Single-ended: in-loop during tap completion, so every reclaimed corridor frees space for the nets routed after it. On the benchmark chain this reclaimed ~150 mm of copper and 21 vias in one step.
• Differential: every committed chain leg gets an island-aware joint re-ask (both polarities, coupled-ness priced into acceptance). Together with new hybrid escape coupling — the first escape leg reserves room for its sibling, the second is strongly attracted alongside — a benchmark pair went from 13% to 77% of its length actually coupled, and a 5 mm redundant spur dissolved into the terminal via it passed anyway.

🚌 Bus routing, rebuilt (Rust 0.18.4/0.18.5)

The bus machinery from 0.18.3 grew up: strict geometric bus detection (parallel cones, comparable lengths, no power nets — 31 sloppy groups became 6 real ones on the benchmark), laminar corridor planning (the corridor probe pays a steep via price, so the planned lane stays on one layer or the group is demoted to plain nets), corridor-span main-edge selection for multipoint members, and a direction-gated multiplicative attraction discount in the Rust router that can't zero out a step cost. Members hug their lane; defectors pay.

🔗 Chains that stay consistent

• Plane-net manifest: the plane steps write a <output>_planes.json sidecar declaring which nets they own; later route/fanout steps auto-exclude those nets from wildcard selection (naming one verbatim still includes it — that's the override). No more accidentally fanning out or signal-routing a net whose plane hasn't poured yet.
• Bare-ball zone exemption: a BGA keep-out that entombs a bare ball of a net the run must route auto-disables for that component — the coverage hole that made some nets structurally unroutable.
• Island-wide launch: multipoint routes may start and land anywhere on a terminal's existing copper island (stub, via, pad — any layer it spans), welded to the actual cell used. Kills the "route retraces its own stub to reach its own via" class.
• Checkpoint snapshots (KICAD_STOP_AFTER=bus, KICAD_STOP_CLEANUP=1) and a per-net story JSON (KICAD_NET_STORY=1: every rip, retry, blocker, and rescue per net) for debugging the journey, not just the destination.

📊 The receipts

Corpus A/B against the 0.18.3-era baselines, zero DRC regressions anywhere, KiCad's own DRC agreeing:

board	before → after
ottercast_audio (benchmark)	5+ unconnected (really 8 by KiCad) → 0 / 0 DRC, fully scripted
mikoto_nrf52840 (aQFN)	3 unconnected → 0 (100%)
dsp_adau1452	1 → 0 (100%)
steppenprobe	1 → 0 (100%, and faster)
ch32v003_usb	1 → 0
hexberry_fpga	100% held, 56 pinched plane islands found & joined

Honesty section, as always: some boards now run ~1.5–3× longer — that's the router attempting work it used to silently skip (truthful gates, island joins, whole-net re-asks). A couple of experimental levers ship opt-in because they graded neutral-or-negative overall despite spectacular individual wins: KICAD_FANOUT_DIRECT=1 (skip fanout stubs for surface-reachable balls — it routed the benchmark's USB pair at 10.7 mm beating the 11.6 mm human reference, but reshuffled the rest of the board) and KICAD_FANOUT_TOWARD_TARGETS=1 (aim escape stubs at their targets). And one net on one keyboard board still resists us. We know where it lives.

Full commit-level detail in the compare view and the Rust changelog in rust_router/README.md.

Bug reports and feedback hugely welcome — open an issue or reply here. Happy routing! 🎉