Reference-plane-void crossing cost: penalize signal tracks crossing pour gaps on the adjacent reference layer

[drandyhaas]

A signal-integrity soft cost rather than a completion one: a signal track crossing OVER a gap in its adjacent reference plane (pour split, void, plane-layer region boundary) breaks its return path — the return current must detour around the void, raising loop inductance, impedance discontinuity, and EMI. Human routers avoid plane-split crossings instinctively; the router today is blind to them and will happily run a controlled-impedance pair straight across a slot.

Sketch

• After planes exist (pours-first chains, Pours-first / no-taps architecture: planes -> plane-aware fanout -> one arbitrated route pass -> repair (worktree-proven, needs graduation) #562), compute per signal layer the VOID MAP of its reference layer(s): cells where the adjacent plane layer(s) have no pour copper (the exact-fill geometry the fragility field already loads gives the real filled polygons — same data source, inverted). Adjacency from the stackup (the impedance machinery already resolves each layer's reference).
• Stamp a moderate cost on signal-layer cells over voids: crossing is discouraged, not banned (a soft cost — sometimes the only route crosses, and a short perpendicular hop over a thin split is the correct engineering compromise anyway).
• Scale by net class: impedance-declared / diff-pair / high-speed nets (the find-high-speed-nets skill's tiers, or --impedance flags) pay full cost; unclassified slow signals a fraction or zero — this field exists for SI, taxing everything would just fight completion.
• Plane fragility (KICAD_PLANE_FRAGILITY) is the complement: it protects the POUR from tracks pinching it; this protects the SIGNAL from the pour's absences. Same geometry source, opposite beneficiary.
• v2: also price running PARALLEL along a split edge (worse than crossing, SI-wise), which needs the direction-aware machinery from Connector-row escape combing: direction-aware field that prices parallel travel through a pin row's escape band #592.

Evaluation

Env-gated; #584 harness for completion NEUTRALITY (it must not cost pads), but the success metric is SI-side: count of void-crossings by impedance/high-speed nets before vs after (a check that belongs in review-routed-board's GND-return audit next to the return-via coverage check). Boards: any with split planes / multiple power pours (zynq_ad9364, ddr5_testbed, lpddr4_testbed).

Refs: #489 §5 ground domains (split-ground awareness precedent), plane fragility field (geometry source), #584 (harness), review-routed-board skill (where the grading check lands).

🤖 Generated with Claude Code

https://claude.ai/code/session_0162EFgykSqFfJgcQxYmR3KB