ports: stm32h723: NO_CACHE in AXI RAM support

Author: dron0gus

firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf_stm32h723.h

@@ -4,9 +4,20 @@
 #ifndef STM32_NOCACHE_ENABLE
 #define STM32_NOCACHE_ENABLE                TRUE
 #endif
+
+#if STM32_NOCACHE_IN_AXI
+// first 16 Kb in AXI SRAM.
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x24000000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+#else
+// whole SRAM2 region.
+// NOTE: this region is not accesable by some bus master
+// For example by SDMMC1 !!!
 #define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
 #define STM32_NOCACHE_RBAR                  0x30002000U
 #define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+#endif
 
 /*
  * PWR system settings.

firmware/hw_layer/ports/stm32/stm32h7/global_port.h

@@ -2,7 +2,11 @@
 #define CCM_OPTIONAL __attribute__((section(".ram5")))
 //TODO: update LD file!
 #define SDRAM_OPTIONAL __attribute__((section(".ram8")))
-// SRAM3 is 32k and set to disable dcache
-#define NO_CACHE __attribute__((aligned(4))) __attribute__((section(".ram3")))
+#if STM32_NOCACHE_IN_AXI
+	#define NO_CACHE __attribute__((aligned(4))) __attribute__((section(".ram0")))
+#else
+	// SRAM3 is 32k and set to disable dcache
+	#define NO_CACHE __attribute__((aligned(4))) __attribute__((section(".ram3")))
+#endif
 
 #define BKUP_RAM_NOINIT __attribute__((section(".bkup_ram_noinit")))