stm32_common: simple way of f42x detection

Author: dron0gus

firmware/hw_layer/ports/mpu_util.h

@@ -18,7 +18,6 @@ void causeHardFault();
 // If mcu can erase/write part of its internal memory without stalling CPU
 bool mcuCanFlashWhileRunning();
 
-bool ramReadProbe(volatile const char *read_address);
 #if defined(STM32F4)
 bool isStm32F42x();
 #endif // STM32F4

firmware/hw_layer/ports/stm32/stm32_common.cpp

@@ -211,60 +211,15 @@ int getRemainingStack(thread_t *otp) {
 #endif /* CH_DBG_ENABLE_STACK_CHECK */
 }
 
-#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HWREG(x)                                                              \
-        (*((volatile unsigned long *)(x)))
-
-#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
-                                            // Fault
-#define NVIC_CFG_CTRL           0xE000ED14  // Configuration and Control
-
-
-/**
- * @brief Probe an address to see if can be read without generating a bus fault
- * @details This function must be called with the processor in privileged mode.
- *          It:
- *          - Clear any previous indication of a bus fault in the BFARV bit
- *          - Temporarily sets the processor to Ignore Bus Faults with all interrupts and fault handlers disabled
- *          - Attempt to read from read_address, ignoring the result
- *          - Checks to see if the read caused a bus fault, by checking the BFARV bit is set
- *          - Re-enables Bus Faults and all interrupts and fault handlers
- * @param[in] read_address The address to try reading a byte from
- * @return Returns true if no bus fault occurred reading from read_address, or false if a bus fault occurred.
- */
-bool ramReadProbe(volatile const char *read_address) {
-    bool address_readable = true;
-
-    /* Clear any existing indication of a bus fault - BFARV is write one to clear */
-    HWREG (NVIC_FAULT_STAT) |= NVIC_FAULT_STAT_BFARV;
-
-    HWREG (NVIC_CFG_CTRL) |= NVIC_CFG_CTRL_BFHFNMIGN;
-    asm volatile ("  CPSID f;");
-    *read_address;
-    if ((HWREG (NVIC_FAULT_STAT) & NVIC_FAULT_STAT_BFARV) != 0)
-    {
-        address_readable = false;
-    }
-    asm volatile ("  CPSIE f;");
-    HWREG (NVIC_CFG_CTRL) &= ~NVIC_CFG_CTRL_BFHFNMIGN;
-
-    return address_readable;
-}
-
-#endif
-
 #if defined(STM32F4)
 bool isStm32F42x() {
-	// really it's enough to just check 0x20020010
-	return ramReadProbe((const char *)0x20000010) && ramReadProbe((const char *)0x20020010) && !ramReadProbe((const char *)0x20070010);
+	// Device identifier
+	// 0x419 for STM32F42xxx and STM32F43xxx
+	// 0x413 for STM32F405xx/07xx and STM32F415xx/17xx
+	return ((DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID_Msk) == 0x419);
 }
-
 #endif
 
-
 // Stubs for per-board low power helpers
 PUBLIC_API_WEAK void boardPrepareForStop() {
 	// Default implementation - wake up on PA0 - boards should override this