Skip to content

Commit 91354bc

Browse files
committed
ports: stm32h7: implement spiCalcClockDiv()
1 parent 25d425a commit 91354bc

2 files changed

Lines changed: 98 additions & 10 deletions

File tree

firmware/hw_layer/hardware.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,19 @@ void stopHardware();
1313

1414
#if HAL_USE_SPI
1515

16+
#ifdef STM32H7XX
17+
18+
#define SPI_BaudRatePrescaler_2 (0x0UL << SPI_CFG1_MBR_Pos)
19+
#define SPI_BaudRatePrescaler_4 (0x1UL << SPI_CFG1_MBR_Pos)
20+
#define SPI_BaudRatePrescaler_8 (0x2UL << SPI_CFG1_MBR_Pos)
21+
#define SPI_BaudRatePrescaler_16 (0x3UL << SPI_CFG1_MBR_Pos)
22+
#define SPI_BaudRatePrescaler_32 (0x4UL << SPI_CFG1_MBR_Pos)
23+
#define SPI_BaudRatePrescaler_64 (0x5UL << SPI_CFG1_MBR_Pos)
24+
#define SPI_BaudRatePrescaler_128 (0x6UL << SPI_CFG1_MBR_Pos)
25+
#define SPI_BaudRatePrescaler_256 (0x7UL << SPI_CFG1_MBR_Pos)
26+
27+
#else /* not STM32H7XX */
28+
1629
// Peripherial Clock 42MHz SPI2 SPI3
1730
// Peripherial Clock 84MHz SPI1 SPI1 SPI2/3
1831
// 42 MHz 21 MHZ
@@ -32,6 +45,8 @@ void stopHardware();
3245
// 328.125 KHz 164.06 KHz
3346
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
3447

48+
#endif
49+
3550
SPIDriver * getSpiDevice(spi_device_e spiDevice);
3651
void turnOnSpi(spi_device_e device);
3752
void lockSpi(spi_device_e device);

firmware/hw_layer/ports/stm32/stm32_spi.cpp

Lines changed: 83 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,89 @@ void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
182182
efiSetPadMode("chip select", csPin, PAL_STM32_MODE_OUTPUT);
183183
}
184184

185+
#ifdef STM32H7XX
186+
187+
int spiGetBaseClock(SPIDriver *spip)
188+
{
189+
#if STM32_SPI_USE_SPI1
190+
if (spip == &SPID1) {
191+
// APB2
192+
return STM32_SPI1CLK;
193+
}
194+
#endif
195+
#if STM32_SPI_USE_SPI2
196+
if (spip == &SPID2) {
197+
// APB1
198+
return STM32_SPI2CLK;
199+
}
200+
#endif
201+
#if STM32_SPI_USE_SPI3
202+
if (spip == &SPID3) {
203+
// APB1
204+
return STM32_SPI3CLK;
205+
}
206+
#endif
207+
#if STM32_SPI_USE_SPI4
208+
if (spip == &SPID4) {
209+
// APB2
210+
return STM32_SPI4CLK;
211+
}
212+
#endif
213+
#if STM32_SPI_USE_SPI5
214+
if (spip == &SPID5) {
215+
// APB2
216+
return STM32_SPI5CLK;
217+
}
218+
#endif
219+
#if STM32_SPI_USE_SPI6
220+
if (spip == &SPID6) {
221+
// APB2
222+
return STM32_SPI6CLK;
223+
}
224+
#endif
225+
226+
return 0;
227+
}
228+
229+
int spiCalcClockDiv(SPIDriver *spip, SPIConfig *spiConfig, unsigned int clk)
230+
{
231+
if (clk == 0) {
232+
return -1;
233+
}
234+
235+
unsigned int baseClock = spiGetBaseClock(spip);
236+
237+
if (baseClock == 0) {
238+
return -1;
239+
}
240+
241+
// round down
242+
int div = (baseClock + clk - 1) / clk;
243+
244+
spiConfig->cfg1 &= ~SPI_CFG1_MBR_Msk;
245+
if (div <= 2) {
246+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_2;
247+
} else if (div <= 4) {
248+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_4;
249+
} else if (div <= 8) {
250+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_8;
251+
} else if (div <= 16) {
252+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_16;
253+
} else if (div <= 32) {
254+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_32;
255+
} else if (div <= 64) {
256+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_64;
257+
} else if (div <= 128) {
258+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_128;
259+
} else {
260+
spiConfig->cfg1 |= SPI_BaudRatePrescaler_256;
261+
}
262+
263+
return 0;
264+
}
265+
266+
#else
267+
185268
int spiGetBaseClock(SPIDriver *spip)
186269
{
187270
#if STM32_SPI_USE_SPI1
@@ -224,16 +307,6 @@ int spiGetBaseClock(SPIDriver *spip)
224307
return 0;
225308
}
226309

227-
#ifdef STM32H7XX
228-
229-
int spiCalcClockDiv(SPIDriver*, SPIConfig*, unsigned int)
230-
{
231-
// TODO: implement
232-
return -1;
233-
}
234-
235-
#else
236-
237310
int spiCalcClockDiv(SPIDriver *spip, SPIConfig *spiConfig, unsigned int clk)
238311
{
239312
if (clk == 0) {

0 commit comments

Comments
 (0)