tb_chain_fb.sv

// tb_chain_fb.sv
// Parameterized full-chain DSSS RX sim for the impairment/robustness campaign.
// Reads an I/Q stim file (+stim=<path>) produced by gen_iq_impaired.py, drives the
// full dsss_rx core, and writes a machine-parseable result file (+out=<path>):
//     framed <0/1>     -- did the PLCP parse (params_valid)?
//     length <n>       -- params_length (payload octets)
//     datarate <n>     -- params_datarate (0 = 1 Mbps)
//     crc <0/1>        -- crc_correct at framer_done
//     done <0/1>       -- did framer_done fire?
//     nbytes <n>       -- decoded data byte count
//     bytes b0 b1 ...  -- decoded payload bytes (LSB-first per byte already)
// Elaborate once (build_snapshot.sh); each sweep point is one xsim run reusing the
// snapshot from an isolated cwd, so hundreds of points fan out cheaply.
`timescale 1ns/1ps
module tb_chain_fb;
    logic               clock = 0, reset = 1;
    logic signed [15:0] sample_i = 0, sample_q = 0;
    logic               sample_valid = 0;
    logic        [12:0] params_length;
    logic        [3:0]  params_datarate;
    logic               params_valid;
    logic        [7:0]  data;
    logic               data_valid, framer_done, crc_correct;

    dsss_rx_fb dut (.clock, .reset, .sample_i, .sample_q, .sample_valid,
                 .params_length, .params_datarate, .params_valid,
                 .data, .data_valid, .framer_done, .crc_correct);

    always #5 clock = ~clock;

    integer fin, fout, r, vi, vq, vv, nbytes = 0;
    integer framed = 0, got_done = 0, got_crc = 0;
    integer cap_len = 0, cap_rate = 0;
    reg [7:0] bytes_arr [0:8191];
    string stimpath, outpath;
    integer i;

    always @(posedge clock) begin
        if (data_valid) begin
            if (nbytes < 8192) bytes_arr[nbytes] = data;
            nbytes = nbytes + 1;
        end
        if (params_valid) begin
            framed   = 1;
            cap_len  = params_length;
            cap_rate = params_datarate;
        end
        if (framer_done) begin
            got_done = 1;
            got_crc  = crc_correct;
        end
    end

    initial begin
        if (!$value$plusargs("stim=%s", stimpath)) begin
            $display("ERROR: need +stim="); $finish;
        end
        if (!$value$plusargs("out=%s", outpath)) begin
            $display("ERROR: need +out="); $finish;
        end
        fin = $fopen(stimpath, "r");
        if (fin == 0) begin $display("ERROR: cannot open %s", stimpath); $finish; end
        @(posedge clock); @(posedge clock); reset = 0;
        while (!$feof(fin)) begin
            r = $fscanf(fin, "%d %d %d", vi, vq, vv);
            if (r != 3) break;
            sample_i = vi[15:0]; sample_q = vq[15:0]; sample_valid = vv[0];
            @(posedge clock);
        end
        sample_valid = 0;
        repeat (100) @(posedge clock);   // drain pipeline / framer_done
        $fclose(fin);

        fout = $fopen(outpath, "w");
        $fwrite(fout, "framed %0d\n", framed);
        $fwrite(fout, "length %0d\n", cap_len);
        $fwrite(fout, "datarate %0d\n", cap_rate);
        $fwrite(fout, "crc %0d\n", got_crc);
        $fwrite(fout, "done %0d\n", got_done);
        $fwrite(fout, "nbytes %0d\n", nbytes);
        $fwrite(fout, "bytes");
        for (i = 0; i < nbytes && i < 8192; i = i + 1)
            $fwrite(fout, " %0d", bytes_arr[i]);
        $fwrite(fout, "\n");
        $fclose(fout);
        $finish;
    end
endmodule