arxml format: start_bit was calculated wrong with case is_little_endian=False, startLittle=True

[pempem98]

This is example:

<I-SIGNAL-TO-I-PDU-MAPPING>
  <SHORT-NAME>isSignalDummy_mtx</SHORT-NAME>
  <I-SIGNAL-REF DEST="I-SIGNAL">/Communication/ISignal/isSignalDummy</I-SIGNAL-REF>
  <PACKING-BYTE-ORDER>MOST-SIGNIFICANT-BYTE-FIRST</PACKING-BYTE-ORDER>
  <START-POSITION>20</START-POSITION>
  <TRANSFER-PROPERTY>PENDING</TRANSFER-PROPERTY>
</I-SIGNAL-TO-I-PDU-MAPPING>

Signal Length = 13
As I check the start bit in DBC file, it showed 24.
By using arxml.py, it showed 19 so I think we have something wrong here.

Order of bits in byte is MSB: 7-6-5-4-3-2-1-0

| Byte 0    | Byte 1    | Byte 2    | Byte 3    | Byte 4    |
|-----------|-----------|-----------|-----------|-----------|
| 0000 0000 | 0000 0000 | 0001 1111 | 1111 1111 | 0000 0000 |

And I think 24 is the correct position so we should correct the calculation here:

canmatrix/src/canmatrix/canmatrix.py

Line 330 in dfe0018

def set_startbit(self, start_bit, bitNumbering=None, startLittle=None):

[pempem98]

canmatrix/src/canmatrix/canmatrix.py

Line 349 in dfe0018

start_bit = start_bit + 1 - self.size

This will be incorrect if the first bit and last bit was not in a same byte

[pempem98]

My proposal:

 def set_startbit(self, start_bit, bitNumbering=None, startLittle=None):
        """
        Set start_bit.

        bitNumbering is 1 for LSB0/LSBFirst, 0 for MSB0/MSBFirst.
        If bit numbering is consistent with byte order (little=LSB0, big=MSB0)
        (KCD, SYM), start bit unmodified.
        Otherwise reverse bit numbering. For DBC, ArXML (OSEK),
        both little endian and big endian use LSB0.
        If bitNumbering is None, assume consistent with byte order.
        If startLittle is set, given start_bit is assumed start from lsb bit
        rather than the start of the signal data in the message data.
        """
        # bit numbering not consistent with byte order. reverse
        if bitNumbering is not None and bitNumbering != self.is_little_endian:
            # if given start_bit is for the end of signal data (lsbit),
            # convert to start of signal data (msbit)
            if startLittle is True and self.is_little_endian is False:
                bits_in_start_byte = start_bit % 8 + 1
                remaining_bits = self.size - bits_in_start_byte
                complement_bits = 8 * ((abs(remaining_bits - 1) // 8) + (1 if remaining_bits > 0 else 0))
                bits_in_end_byte = 8 if (remaining_bits % 8) == 0 else remaining_bits % 8
                start_bit = start_bit - (bits_in_start_byte - 1) + complement_bits + (8 - bits_in_end_byte)
            else:
                start_bit = start_bit - (start_bit % 8) + 7 - (start_bit % 8)
        if start_bit < 0:
            raise StartbitLowerZero(
                "wrong start_bit found Signal: %s Startbit: %d" % (self.name, start_bit)
            )
        self.start_bit = start_bit

[ebroecker]

Hi @pempem98,

I tried to reproduce this issue with following example-arxml:

example.zip

Not sure if I missed something, but I was not able to reproduce...