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nascstingleby
nascs
authored and
tingleby
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platform: fix the pwm function of radxa boards
Signed-off-by: Nascs <[email protected]>
1 parent 4e11858 commit 9374cc4

9 files changed

+20
-17
lines changed

‎include/arm/radxa_cm5_io.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ extern "C" {
1717
#define MRAA_RADXA_CM5_IO_I2C_COUNT 4
1818
#define MRAA_RADXA_CM5_IO_SPI_COUNT 1
1919
#define MRAA_RADXA_CM5_IO_UART_COUNT 2
20-
#define MRAA_RADXA_CM5_IO_PWM_COUNT 7
20+
#define MRAA_RADXA_CM5_IO_PWM_COUNT 9
2121
#define MRAA_RADXA_CM5_IO_AIO_COUNT 1
2222
#define MRAA_RADXA_CM5_IO_PIN_COUNT 40
2323
#define PLATFORM_NAME_RADXA_CM5_IO "Radxa CM5 IO"

‎include/arm/radxa_rock_3c.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ extern "C" {
1717
#define MRAA_RADXA_ROCK_3C_I2C_COUNT 2
1818
#define MRAA_RADXA_ROCK_3C_SPI_COUNT 1
1919
#define MRAA_RADXA_ROCK_3C_UART_COUNT 5
20-
#define MRAA_RADXA_ROCK_3C_PWM_COUNT 7
20+
#define MRAA_RADXA_ROCK_3C_PWM_COUNT 6
2121
#define MRAA_RADXA_ROCK_3C_AIO_COUNT 0
2222
#define MRAA_RADXA_ROCK_3C_PIN_COUNT 40
2323
#define PLATFORM_NAME_RADXA_ROCK_3C "Radxa ROCK3 Model C"

‎include/arm/radxa_rock_5b.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ extern "C" {
1717
#define MRAA_RADXA_ROCK_5B_I2C_COUNT 4
1818
#define MRAA_RADXA_ROCK_5B_SPI_COUNT 2
1919
#define MRAA_RADXA_ROCK_5B_UART_COUNT 4
20-
#define MRAA_RADXA_ROCK_5B_PWM_COUNT 10
20+
#define MRAA_RADXA_ROCK_5B_PWM_COUNT 14
2121
#define MRAA_RADXA_ROCK_5B_AIO_COUNT 1
2222
#define MRAA_RADXA_ROCK_5B_PIN_COUNT 40
2323
#define PLATFORM_NAME_RADXA_ROCK_5B "Radxa ROCK 5B"

‎src/arm/radxa_cm3.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,8 @@ mraa_radxa_cm3()
110110
b->pins[31].pwm.mux_total = 0;
111111
b->pins[32].pwm.parent_id = 11; // pwm11-m1
112112
b->pins[32].pwm.mux_total = 0;
113-
b->pins[33].pwm.parent_id = 15; // pwm7
113+
b->pins[32].pwm.pinmap = 0;
114+
b->pins[33].pwm.parent_id = 7; // pwm7
114115
b->pins[33].pwm.mux_total = 0;
115116
b->pins[37].pwm.parent_id = 3; // pwm3
116117
b->pins[37].pwm.mux_total = 0;

‎src/arm/radxa_cm5_io.c

+8-2
Original file line numberDiff line numberDiff line change
@@ -90,12 +90,18 @@ mraa_radxa_cm5_io()
9090
return NULL;
9191
}
9292

93+
b->pins[3].pwm.parent_id = 10; // PWM10-M2
94+
b->pins[3].pwm.mux_total = 0;
95+
b->pins[3].pwm.pinmap = 0;
9396
b->pins[16].pwm.parent_id = 11; // PWM11-M0
9497
b->pins[16].pwm.mux_total = 0;
9598
b->pins[16].pwm.pinmap = 0;
96-
b->pins[24].pwm.parent_id = 11; // PWM14-M1
99+
b->pins[24].pwm.parent_id = 14; // PWM14-M1
97100
b->pins[24].pwm.mux_total = 0;
98101
b->pins[24].pwm.pinmap = 0;
102+
b->pins[28].pwm.parent_id = 14; // PWM14-M2
103+
b->pins[28].pwm.mux_total = 0;
104+
b->pins[28].pwm.pinmap = 0;
99105
b->pins[29].pwm.parent_id = 7; // PWM7-M0
100106
b->pins[29].pwm.mux_total = 0;
101107
b->pins[29].pwm.pinmap = 0;
@@ -123,7 +129,7 @@ mraa_radxa_cm5_io()
123129
mraa_radxa_cm5_io_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
124130
mraa_radxa_cm5_io_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
125131
mraa_radxa_cm5_io_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
126-
mraa_radxa_cm5_io_pininfo(b, 3, 3, 27, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D3");
132+
mraa_radxa_cm5_io_pininfo(b, 3, 3, 27, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO3_D3");
127133
mraa_radxa_cm5_io_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "5V");
128134
mraa_radxa_cm5_io_pininfo(b, 5, 3, 26, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D2");
129135
mraa_radxa_cm5_io_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");

‎src/arm/radxa_rock_3a.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,6 @@ mraa_radxa_rock_3a()
9999
return NULL;
100100
}
101101

102-
b->pins[7].pwm.parent_id = 12; // PWM12_M0
103-
b->pins[7].pwm.mux_total = 0;
104102
b->pins[7].pwm.parent_id = 1; // PWM1_M1
105103
b->pins[7].pwm.mux_total = 0;
106104
b->pins[11].pwm.parent_id = 14; // PWM14_M0
@@ -117,6 +115,8 @@ mraa_radxa_rock_3a()
117115
b->pins[19].pwm.mux_total = 0;
118116
b->pins[21].pwm.parent_id = 12; // PWM12_M1
119117
b->pins[21].pwm.mux_total = 0;
118+
b->pins[22].pwm.parent_id = 2; // PWM2_M0
119+
b->pins[22].pwm.mux_total = 0;
120120
b->pins[23].pwm.parent_id = 14; // PWM14_M1
121121
b->pins[23].pwm.mux_total = 0;
122122
b->pins[24].pwm.parent_id = 13; // PWM13_M1

‎src/arm/radxa_rock_3c.c

+1-5
Original file line numberDiff line numberDiff line change
@@ -96,14 +96,10 @@ mraa_radxa_rock_3c()
9696

9797
b->pins[7].pwm.parent_id = 14; // pwm14-m0
9898
b->pins[7].pwm.mux_total = 0;
99-
b->pins[13].pwm.parent_id = 15; // pwm15-m0
100-
b->pins[13].pwm.mux_total = 0;
10199
b->pins[16].pwm.parent_id = 8; // pwm8-m0
102100
b->pins[16].pwm.mux_total = 0;
103101
b->pins[18].pwm.parent_id = 9; // pwm9-m0
104102
b->pins[18].pwm.mux_total = 0;
105-
b->pins[19].pwm.parent_id = 15; // pwm15-m1
106-
b->pins[19].pwm.mux_total = 0;
107103
b->pins[21].pwm.parent_id = 12; // pwm12-m1
108104
b->pins[21].pwm.mux_total = 0;
109105
b->pins[23].pwm.parent_id = 14; // pwm14-m1
@@ -130,7 +126,7 @@ mraa_radxa_rock_3c()
130126
mraa_radxa_rock_3c_pininfo(b, 16, 3, 9, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO03_B1");
131127
mraa_radxa_rock_3c_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
132128
mraa_radxa_rock_3c_pininfo(b, 18, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2");
133-
mraa_radxa_rock_3c_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C3");
129+
mraa_radxa_rock_3c_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_C3"); // Pwm 15 channel 0 used by fan0
134130
mraa_radxa_rock_3c_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
135131
mraa_radxa_rock_3c_pininfo(b, 21, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C5");
136132
mraa_radxa_rock_3c_pininfo(b, 22, 3, 17, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_C1");

‎src/arm/radxa_rock_5a.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -116,15 +116,15 @@ mraa_radxa_rock_5a()
116116
b->pins[23].pwm.parent_id = 0; // PWM0_M2
117117
b->pins[23].pwm.mux_total = 0;
118118
b->pins[23].pwm.pinmap = 0;
119+
b->pins[24].pwm.parent_id = 1; // PWM1_M2
120+
b->pins[24].pwm.mux_total = 0;
121+
b->pins[24].pwm.pinmap = 0;
119122
b->pins[27].pwm.parent_id = 6; // PWM6_M0
120123
b->pins[27].pwm.mux_total = 0;
121124
b->pins[27].pwm.pinmap = 0;
122125
b->pins[28].pwm.parent_id = 7; // PWM7_M0
123126
b->pins[28].pwm.mux_total = 0;
124127
b->pins[28].pwm.pinmap = 0;
125-
b->pins[28].pwm.parent_id = 1; // PWM1_M2
126-
b->pins[28].pwm.mux_total = 0;
127-
b->pins[28].pwm.pinmap = 0;
128128

129129
// AIO
130130
b->aio_count = MRAA_RADXA_ROCK_5A_AIO_COUNT;

‎src/arm/radxa_rock_5b.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ mraa_radxa_rock_5b()
108108
b->pins[28].pwm.parent_id = 6; // PWM6_M2
109109
b->pins[28].pwm.mux_total = 0;
110110
b->pins[28].pwm.pinmap = 0;
111-
b->pins[29].pwm.parent_id = 7; // PWM15_M3
111+
b->pins[29].pwm.parent_id = 15; // PWM15_M3
112112
b->pins[29].pwm.mux_total = 0;
113113
b->pins[29].pwm.pinmap = 0;
114114
b->pins[31].pwm.parent_id = 13; // PWM13_M2

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