- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. WCED [%] and # LUTs parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | PowerW | Delayns | LUTs | Download |
|---|---|---|---|---|---|---|---|---|---|
| add12u_0NB | 0.00 | 0.00 | 0.00 | 0.00 | 0 | 0.42 | 9.8 | 12 | [Verilog] [VerilogPDK45] [C] |
| add12u_074 | 0.012 | 0.024 | 75.00 | 0.034 | 1.5 | 0.4 | 9.7 | 10 | [Verilog] [VerilogPDK45] [C] |
| add12u_0M4 | 0.024 | 0.049 | 87.50 | 0.068 | 5.5 | 0.38 | 8.6 | 9.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_09A | 0.049 | 0.11 | 93.75 | 0.14 | 22 | 0.38 | 8.5 | 8.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0M8 | 0.098 | 0.20 | 99.22 | 0.27 | 76 | 0.36 | 8.3 | 7.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0KX | 0.39 | 0.78 | 99.80 | 1.08 | 1340 | 0.33 | 7.6 | 5.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0KY | 0.78 | 1.56 | 99.95 | 2.15 | 4968 | 0.32 | 6.7 | 4.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0FQ | 1.63 | 4.26 | 99.82 | 4.51 | 24520 | 0.3 | 6.7 | 3.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_00J | 3.25 | 9.11 | 99.91 | 9.07 | 97656 | 0.3 | 6.3 | 2.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_1JB | 12.50 | 25.00 | 100.00 | 30.48 | 13286.96e2 | 0.27 | 5.1 | 0 | [Verilog] [VerilogPDK45] [C] |
PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.