README.md

Selected circuits

• Circuit: 8-bit unsigned adders
• Selection criteria: pareto optimal sub-set wrt. MED [%] and Latency parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	PowerW	Delayns	LUTs	Download
add8u_2LQ	0.098	0.20	50.00	0.27	0.5	0.35	7.0	11	[Verilog] [VerilogPDK45] [C]
add8u_174	0.20	0.39	75.00	0.54	1.5	0.35	6.9	8.0	[Verilog] [VerilogPDK45] [C]
add8u_0B1	0.55	1.37	87.50	1.50	12	0.31	6.7	5.0	[Verilog] [VerilogPDK45] [C]
add8u_01E	0.82	2.15	93.75	2.28	24	0.31	6.6	6.0	[Verilog] [VerilogPDK45] [C]
add8u_04G	1.04	3.32	94.24	2.81	42	0.3	6.3	4.0	[Verilog] [VerilogPDK45] [C]
add8u_01X	1.93	6.45	97.02	5.96	148	0.29	6.0	3.0	[Verilog] [VerilogPDK45] [C]
add8u_0AX	4.43	14.84	98.65	12.37	775	0.28	6.0	3.0	[Verilog] [VerilogPDK45] [C]
add8u_06S	6.48	17.77	99.22	16.90	1520	0.28	5.8	2.0	[Verilog] [VerilogPDK45] [C]
add8u_04A	14.06	42.38	99.61	35.29	7477	0.26	4.9	0	[Verilog] [VerilogPDK45] [C]

Parameters

References

PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.